Home
last modified time | relevance | path

Searched refs:fcvtzu (Results 1 – 25 of 98) sorted by relevance

1234

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dfcvtzu.s10 fcvtzu z0.h, p0/m, z0.h label
16 fcvtzu z0.s, p0/m, z0.h label
22 fcvtzu z0.s, p0/m, z0.s label
28 fcvtzu z0.s, p0/m, z0.d label
34 fcvtzu z0.d, p0/m, z0.h label
40 fcvtzu z0.d, p0/m, z0.s label
46 fcvtzu z0.d, p0/m, z0.d label
62 fcvtzu z5.d, p0/m, z0.d label
74 fcvtzu z5.d, p0/m, z0.d label
Dfcvtzu-diagnostics.s3 fcvtzu z0.h, p0/m, z0.s label
8 fcvtzu z0.h, p0/m, z0.d label
17 fcvtzu z0.h, p8/m, z0.h label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s69 fcvtzu h21, h12, #1
70 fcvtzu s21, s12, #1
71 fcvtzu d21, d12, #1
207 fcvtzu h12, h13
208 fcvtzu s12, s13
209 fcvtzu d21, d14
Darm64-fp-encoding.s432 fcvtzu w1, h2
433 fcvtzu w1, h2, #1
434 fcvtzu w1, s2
435 fcvtzu w1, s2, #1
436 fcvtzu w1, d2
437 fcvtzu w1, d2, #1
438 fcvtzu x1, h2
439 fcvtzu x1, h2, #1
440 fcvtzu x1, s2
441 fcvtzu x1, s2, #1
[all …]
Dneon-simd-shift.s433 fcvtzu v0.4h, v1.4h, #3
434 fcvtzu v0.8h, v1.8h, #3
435 fcvtzu v0.2s, v1.2s, #3
436 fcvtzu v0.4s, v1.4s, #3
437 fcvtzu v0.2d, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s69 fcvtzu h21, h12, #1
70 fcvtzu s21, s12, #1
71 fcvtzu d21, d12, #1
207 fcvtzu h12, h13
208 fcvtzu s12, s13
209 fcvtzu d21, d14
Darm64-fp-encoding.s432 fcvtzu w1, h2
433 fcvtzu w1, h2, #1
434 fcvtzu w1, s2
435 fcvtzu w1, s2, #1
436 fcvtzu w1, d2
437 fcvtzu w1, d2, #1
438 fcvtzu x1, h2
439 fcvtzu x1, h2, #1
440 fcvtzu x1, s2
441 fcvtzu x1, s2, #1
[all …]
Dneon-simd-shift.s433 fcvtzu v0.4h, v1.4h, #3
434 fcvtzu v0.8h, v1.8h, #3
435 fcvtzu v0.2s, v1.2s, #3
436 fcvtzu v0.4s, v1.4s, #3
437 fcvtzu v0.2d, v1.2d, #3
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs12 0x95,0xfd,0x3f,0x7f = fcvtzu s21, s12, #1
13 0x95,0xfd,0x7f,0x7f = fcvtzu d21, d12, #1
33 0xac,0xb9,0xa1,0x7e = fcvtzu s12, s13
34 0xd5,0xb9,0xe1,0x7e = fcvtzu d21, d14
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfcvt-fixed.ll61 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #7
66 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #32
71 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #7
76 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #64
81 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #7
86 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #32
91 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #7
96 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-2012-06-06-FPToUI.ll11 ; CHECK: fcvtzu x{{[0-9]+}}, d{{[0-9]+}}
12 ; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
31 ; CHECK: fcvtzu x{{[0-9]+}}, s{{[0-9]+}}
32 ; CHECK: fcvtzu w{{[0-9]+}}, s{{[0-9]+}}
Darm64-cvt.ll368 ;CHECK: fcvtzu w0, s0
370 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %A)
376 ;CHECK: fcvtzu x0, s0
378 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)
384 ;CHECK: fcvtzu w0, d0
386 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)
392 ;CHECK: fcvtzu x0, d0
394 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %A)
398 declare i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float) nounwind readnone
399 declare i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float) nounwind readnone
[all …]
Dvcvt-oversize.ll8 ; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s
9 ; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s
Dfcvt-int.ll8 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}}
23 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}}
38 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}}
53 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll13 ; CHECK: fcvtzu.2s v0, v0
29 ; CHECK: fcvtzu.4s v0, v0
Dfcvt_combine.ll72 ; CHECK: fcvtzu.2s v0, v0, #4
84 ; CHECK: fcvtzu.2s v0, v0
95 ; CHECK: fcvtzu.2s v0, v0
105 ; CHECK: fcvtzu.2s v{{[0-9]+}}, v{{[0-9]+}}
115 ; CHECK: fcvtzu.2s v0, v0, #3
Dcomplex-fp-to-int.ll15 ; CHECK: fcvtzu.2d v0, [[VAL64]]
64 ; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
100 ; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0
/external/llvm/test/CodeGen/AArch64/
Dfcvt-fixed.ll61 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #7
66 ; CHECK: fcvtzu {{w[0-9]+}}, {{s[0-9]+}}, #32
71 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #7
76 ; CHECK: fcvtzu {{x[0-9]+}}, {{s[0-9]+}}, #64
81 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #7
86 ; CHECK: fcvtzu {{w[0-9]+}}, {{d[0-9]+}}, #32
91 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #7
96 ; CHECK: fcvtzu {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-2012-06-06-FPToUI.ll11 ; CHECK: fcvtzu x{{[0-9]+}}, d{{[0-9]+}}
12 ; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
31 ; CHECK: fcvtzu x{{[0-9]+}}, s{{[0-9]+}}
32 ; CHECK: fcvtzu w{{[0-9]+}}, s{{[0-9]+}}
Darm64-cvt.ll368 ;CHECK: fcvtzu w0, s0
370 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %A)
376 ;CHECK: fcvtzu x0, s0
378 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)
384 ;CHECK: fcvtzu w0, d0
386 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)
392 ;CHECK: fcvtzu x0, d0
394 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %A)
398 declare i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float) nounwind readnone
399 declare i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float) nounwind readnone
[all …]
Dvcvt-oversize.ll8 ; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s
9 ; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s
Dfcvt-int.ll8 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}}
23 ; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}}
38 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}}
53 ; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll13 ; CHECK: fcvtzu.2s v0, v0
29 ; CHECK: fcvtzu.4s v0, v0
Dfcvt_combine.ll72 ; CHECK: fcvtzu.2s v0, v0, #4
84 ; CHECK: fcvtzu.2s v0, v0
95 ; CHECK: fcvtzu.2s v0, v0
106 ; CHECK: fcvtzu.2s v{{[0-9]+}}, v{{[0-9]+}}
116 ; CHECK: fcvtzu.2s v0, v0, #3
Dcomplex-fp-to-int.ll15 ; CHECK: fcvtzu.2d v0, [[VAL64]]
64 ; CHECK: fcvtzu.4s [[VAL64:v[0-9]+]], v0
100 ; CHECK: fcvtzu.2d [[VAL64:v[0-9]+]], v0

1234