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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dflat-gfx9.s8 flat_load_dword v1, v[3:4] offset:0 label
11 flat_load_dword v1, v[3:4] offset:-1 label
15 flat_load_dword v1, v[3:4] offset:4095 label
19 flat_load_dword v1, v[3:4] offset:4096 label
22 flat_load_dword v1, v[3:4] offset:4 glc label
26 flat_load_dword v1, v[3:4] offset:4 glc slc label
103 flat_load_dword v1, v[3:4], off label
106 flat_load_dword v1, v[3:4], s[0:1] label
109 flat_load_dword v1, v[3:4], s0 label
112 flat_load_dword v1, v[3:4], exec_hi label
Dreg-syntax-extra.s93 flat_load_dword v[8:8], v[2:3] label
96 flat_load_dword v[63/8+1:65/8], v[2:3] label
99 flat_load_dword v8, v[2*2-2:(3+7)/3] label
102 flat_load_dword v[63/8+1], v[2:3] label
Dflat.s18 flat_load_dword v1, v[3:4] label
23 flat_load_dword v1, v[3:4] glc label
28 flat_load_dword v1, v[3:4] glc slc label
89 flat_load_dword v1, v[3:4] label
Dmacro-examples.s11 flat_load_dword v[8 + \iter], v[2:3]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dmemory-legalizer-load.ll10 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
24 ; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
38 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
52 ; GCN-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
66 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
80 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
94 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
108 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
122 ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
136 ; GFX89: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
[all …]
Dsdwa-preserve.mir6 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
7 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
60 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
61 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
104 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
105 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
Dglobal-variable-relocs.ll21 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
35 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
52 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
69 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
86 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
103 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
120 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
137 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
154 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
171 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
[all …]
Dllvm.amdgcn.implicitarg.ptr.ll68 ; HSA: flat_load_dword v0, v[0:1]
86 ; HSA: flat_load_dword v0, v[0:1]
173 ; HSA: flat_load_dword v0, v[0:1]
179 ; HSA: flat_load_dword v0, v[0:1]
200 ; HSA: flat_load_dword v0, v[0:1]
206 ; HSA: flat_load_dword v0, v[0:1]
Dglobal-smrd-unknown.ll4 ; GCN: flat_load_dword
5 ; GCN: flat_load_dword
Dipra.ll25 ; GCN: flat_load_dword v8
47 ; GCN: flat_load_dword v8
79 ; GCN: flat_load_dword v8
Dsub.v2i16.ll110 ; VI-DAG: flat_load_dword [[LOAD:v[0-9]+]]
127 ; VI: flat_load_dword [[LOAD:v[0-9]+]]
148 ; VI: flat_load_dword
172 ; VI: flat_load_dword v[[A:[0-9]+]]
173 ; VI: flat_load_dword v[[B:[0-9]+]]
202 ; VI: flat_load_dword [[A:v[0-9]+]]
203 ; VI: flat_load_dword [[B:v[0-9]+]]
230 ; VI: flat_load_dword
231 ; VI: flat_load_dword
Dwaitcnt-flat.ll5 ; If flat_store_dword and flat_load_dword use different registers for the data
12 ; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}]
Dglobal_smrd.ll6 ; CHECK-NOT: flat_load_dword
28 ; CHECK: flat_load_dword
72 ; CHECK: flat_load_dword [[VVAL:v[0-9]+]]
107 ; CHECK: flat_load_dword [[VVAL:v[0-9]+]], [[A_ADDR]]
Dglobal_smrd_cfg.ll7 ; CHECK: flat_load_dword
18 ; CHECK: flat_load_dword
84 ; CHECK: flat_load_dword
Dadd.v2i16.ll109 ; VI: flat_load_dword [[LOAD:v[0-9]+]]
126 ; VI: flat_load_dword
172 ; VI: flat_load_dword v[[A:[0-9]+]]
173 ; VI: flat_load_dword v[[B:[0-9]+]]
206 ; VI: flat_load_dword v[[A:[0-9]+]]
207 ; VI: flat_load_dword v[[B:[0-9]+]]
Dinline-constraints.ll5 ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
19 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
/external/llvm/test/MC/AMDGPU/
Dflat.s18 flat_load_dword v1, v[3:4] label
23 flat_load_dword v1, v[3:4] glc label
28 flat_load_dword v1, v[3:4] glc slc label
33 flat_load_dword v1, v[3:4] glc tfe label
38 flat_load_dword v1, v[3:4] glc slc tfe label
43 flat_load_dword v1, v[3:4] slc label
48 flat_load_dword v1, v[3:4] slc tfe label
53 flat_load_dword v1, v[3:4] tfe label
154 flat_load_dword v1, v[3:4] label
Dreg-syntax-extra.s93 flat_load_dword v[8:8], v[2:3] label
96 flat_load_dword v[63/8+1:65/8], v[2:3] label
99 flat_load_dword v8, v[2*2-2:(3+7)/3] label
102 flat_load_dword v[63/8+1], v[2:3] label
Dmacro-examples.s11 flat_load_dword v[8 + \iter], v[2:3]
/external/llvm/test/CodeGen/AMDGPU/
Dglobal-variable-relocs.ll21 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
35 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
52 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
69 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
86 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
103 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
120 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
137 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
154 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
171 ; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
[all …]
Dwaitcnt-flat.ll4 ; If flat_store_dword and flat_load_dword use different registers for the data
11 ; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}]
Dinline-constraints.ll5 ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
15 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
/external/llvm/test/MC/Disassembler/AMDGPU/
Dflat_vi.txt3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
15 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
18 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
21 # VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
24 # VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
57 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dflat_gfx9.txt27 # CHECK: flat_load_dword v0, v[0:1] ; encoding: [0x00,0x00,0x50,0xdc,0x00,0x00,0x00,0x00]
30 # CHECK: flat_load_dword v0, v[0:1] offset:7 ; encoding: [0x07,0x00,0x50,0xdc,0x00,0x00,0x00,0x0…
33 # CHECK: flat_load_dword v0, v[0:1] offset:4095 glc ; encoding: [0xff,0x0f,0x51,0xdc,0x00,0x00,0…
Dflat_vi.txt3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
33 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]

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