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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
DPBQP-chain.ll9 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
10 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
11 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
12 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
13 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
14 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
15 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
16 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
17 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
18 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
[all …]
Daarch64-a57-fp-load-balancing.ll29 ; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
30 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
31 ; CHECK: fmadd [[x]]
33 ; CHECK: fmadd [[x]]
75 ; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
77 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
79 ; CHECK: fmadd [[x]]
80 ; CHECK: fmadd [[y]]
82 ; CHECK: fmadd [[y]]
83 ; CHECK: fmadd [[x]]
[all …]
Dfp-dp3.ll11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
51 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
52 ; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
92 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
93 ; CHECK-NOFAST-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
145 ; CHECK-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
Darm64-fmuladd.ll5 ;CHECK: fmadd
6 ;CHECK-NOT: fmadd
50 ;CHECK: fmadd
51 ;CHECK-NOT: fmadd
/external/llvm/test/CodeGen/AArch64/
DPBQP-chain.ll9 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
10 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
11 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
12 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
13 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
14 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
15 ; CHECK-EVEN: fmadd {{d[0-9]*[02468]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[02468]}}
16 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
17 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
18 ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}}
[all …]
Daarch64-a57-fp-load-balancing.ll29 ; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
30 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
31 ; CHECK: fmadd [[x]]
33 ; CHECK: fmadd [[x]]
75 ; CHECK-EVEN: fmadd [[x:d[0-9]*[02468]]]
77 ; CHECK-ODD: fmadd [[x:d[0-9]*[13579]]]
79 ; CHECK: fmadd [[x]]
80 ; CHECK: fmadd [[y]]
82 ; CHECK: fmadd [[y]]
83 ; CHECK: fmadd [[x]]
[all …]
Dfp-dp3.ll11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
51 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
52 ; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
92 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
93 ; CHECK-NOFAST-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
145 ; CHECK-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
Darm64-fmuladd.ll5 ;CHECK: fmadd
6 ;CHECK-NOT: fmadd
50 ;CHECK: fmadd
51 ;CHECK-NOT: fmadd
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfma-assoc.ll15 ; CHECK-SAFE-NEXT: fmadd
20 ; CHECK-UNSAFE: fmadd
21 ; CHECK-UNSAFE-NEXT: fmadd
46 ; CHECK-SAFE-NEXT: fmadd
51 ; CHECK-UNSAFE: fmadd
52 ; CHECK-UNSAFE-NEXT: fmadd
77 ; CHECK-SAFE-NEXT: fmadd
83 ; CHECK-UNSAFE-NEXT: fmadd
108 ; CHECK-SAFE-NEXT: fmadd
139 ; CHECK: fmadd
[all …]
Dvec_fmuladd.ll44 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
45 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
53 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
54 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
55 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
56 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
Drecipest.ll20 ; CHECK-NEXT: fmadd
23 ; CHECK-NEXT: fmadd
41 ; CHECK-NOT: fmadd
43 ; CHECK-NOT: fmadd
79 ; CHECK-NEXT: fmadd
82 ; CHECK-NEXT: fmadd
176 ; CHECK: fmadd
178 ; CHECK-NEXT: fmadd
224 ; CHECK-NEXT: fmadd
227 ; CHECK-NEXT: fmadd
/external/llvm/test/CodeGen/PowerPC/
Dfma-assoc.ll12 ; CHECK: fmadd
13 ; CHECK-NEXT: fmadd
31 ; CHECK: fmadd
32 ; CHECK-NEXT: fmadd
51 ; CHECK-NEXT: fmadd
89 ; CHECK: fmadd
90 ; CHECK-NEXT: fmadd
108 ; CHECK: fmadd
109 ; CHECK-NEXT: fmadd
128 ; CHECK: fmadd
[all …]
Dvec_fmuladd.ll44 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
45 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
53 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
54 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
55 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
56 ; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
Drecipest.ll20 ; CHECK-NEXT: fmadd
23 ; CHECK-NEXT: fmadd
30 ; CHECK-NONR-NOT: fmadd
32 ; CHECK-NONR-NOT: fmadd
72 ; CHECK-NEXT: fmadd
75 ; CHECK-NEXT: fmadd
162 ; CHECK: fmadd
164 ; CHECK-NEXT: fmadd
210 ; CHECK-NEXT: fmadd
213 ; CHECK-NEXT: fmadd
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/external/llvm/test/CodeGen/Mips/msa/
D3rf_4rf.ll17 %3 = tail call <4 x float> @llvm.mips.fmadd.w(<4 x float> %0, <4 x float> %1, <4 x float> %2)
22 declare <4 x float> @llvm.mips.fmadd.w(<4 x float>, <4 x float>, <4 x float>) nounwind
28 ; CHECK: fmadd.w
42 %3 = tail call <2 x double> @llvm.mips.fmadd.d(<2 x double> %0, <2 x double> %1, <2 x double> %2)
47 declare <2 x double> @llvm.mips.fmadd.d(<2 x double>, <2 x double>, <2 x double>) nounwind
53 ; CHECK: fmadd.d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Drv32f-valid.s44 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
46 fmadd.s f10, f11, f12, f13, dyn
120 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, rne
122 fmadd.s f10, f11, f12, f13, rne
132 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, rmm
134 fmadd.s f10, f11, f12, f13, rmm
Drv32d-valid.s49 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
51 fmadd.d f10, f11, f12, f13, dyn
124 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, rne
126 fmadd.d f10, f11, f12, f13, rne
Drvd-aliases-valid.s50 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
51 # CHECK-ALIAS: fmadd.d fa0, fa1, fa2, fa3{{[[:space:]]}}
52 fmadd.d f10, f11, f12, f13
Drv32f-invalid.s24 fmadd.s f10, f11, f12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
27 fmadd.s f10, f11, f12, f13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating poi…
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-fp.s.cs59 0xfc,0x43,0x29,0x3a = fmadd 2, 3, 4, 5
60 0xfc,0x43,0x29,0x3b = fmadd. 2, 3, 4, 5
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s194 # CHECK-BE: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a]
195 # CHECK-LE: fmadd 2, 3, 4, 5 # encoding: [0x3a,0x29,0x43,0xfc]
196 fmadd 2, 3, 4, 5
197 # CHECK-BE: fmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3b]
198 # CHECK-LE: fmadd. 2, 3, 4, 5 # encoding: [0x3b,0x29,0x43,0xfc]
199 fmadd. 2, 3, 4, 5
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s200 # CHECK-BE: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a]
201 # CHECK-LE: fmadd 2, 3, 4, 5 # encoding: [0x3a,0x29,0x43,0xfc]
202 fmadd 2, 3, 4, 5
203 # CHECK-BE: fmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3b]
204 # CHECK-LE: fmadd. 2, 3, 4, 5 # encoding: [0x3b,0x29,0x43,0xfc]
205 fmadd. 2, 3, 4, 5
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfp-contract.ll1 ; Test that the compiled does not fuse fmul and fadd into fmadd when no -fp-contract=fast
23 ; CHECK-CONTRACT-FAST: fmadd.w
/external/llvm/test/MC/Mips/msa/
Dtest_3rf.s33 # CHECK: fmadd.w $w29, $w6, $w23 # encoding: [0x79,0x17,0x37,0x5b]
34 # CHECK: fmadd.d $w11, $w28, $w21 # encoding: [0x79,0x35,0xe2,0xdb]
116 fmadd.w $w29, $w6, $w23
117 fmadd.d $w11, $w28, $w21

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