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Searched refs:fmask_state (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_image.c392 uint32_t *fmask_state) in si_make_texture_descriptor() argument
539 fmask_state[0] = va >> 8; in si_make_texture_descriptor()
540 fmask_state[0] |= image->fmask.tile_swizzle; in si_make_texture_descriptor()
541 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | in si_make_texture_descriptor()
544 fmask_state[2] = S_008F18_WIDTH(width - 1) | in si_make_texture_descriptor()
546 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | in si_make_texture_descriptor()
551 fmask_state[4] = 0; in si_make_texture_descriptor()
552 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer); in si_make_texture_descriptor()
553 fmask_state[6] = 0; in si_make_texture_descriptor()
554 fmask_state[7] = 0; in si_make_texture_descriptor()
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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state.c3545 uint32_t *fmask_state) in si_make_texture_descriptor() argument
3784 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle; in si_make_texture_descriptor()
3785 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | in si_make_texture_descriptor()
3788 fmask_state[2] = S_008F18_WIDTH(width - 1) | in si_make_texture_descriptor()
3790 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | in si_make_texture_descriptor()
3795 fmask_state[4] = 0; in si_make_texture_descriptor()
3796 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer); in si_make_texture_descriptor()
3797 fmask_state[6] = 0; in si_make_texture_descriptor()
3798 fmask_state[7] = 0; in si_make_texture_descriptor()
3801 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); in si_make_texture_descriptor()
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Dsi_state.h390 uint32_t *fmask_state);
Dsi_pipe.h230 uint32_t fmask_state[8]; member
Dsi_descriptors.c463 memcpy(desc + 8, sview->fmask_state, 8*4); in si_set_sampler_view_desc()