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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dfmaxnm.s10 fmaxnm z0.h, p0/m, z0.h, #0.000000000000000 label
16 fmaxnm z0.h, p0/m, z0.h, #0.0 label
22 fmaxnm z0.s, p0/m, z0.s, #0.0 label
28 fmaxnm z0.d, p0/m, z0.d, #0.0 label
34 fmaxnm z31.h, p7/m, z31.h, #1.000000000000000 label
40 fmaxnm z31.h, p7/m, z31.h, #1.0 label
46 fmaxnm z31.s, p7/m, z31.s, #1.0 label
52 fmaxnm z31.d, p7/m, z31.d, #1.0 label
58 fmaxnm z0.h, p7/m, z0.h, z31.h label
64 fmaxnm z0.s, p7/m, z0.s, z31.s label
[all …]
Dfmaxnm-diagnostics.s6 fmaxnm z0.h, p0/m, z0.h, #0.5 label
11 fmaxnm z0.h, p0/m, z0.h, #-0.0 label
16 fmaxnm z0.h, p0/m, z0.h, #0.0000000000000000000000001 label
21 fmaxnm z0.h, p0/m, z0.h, #1.0000000000000000000000001 label
26 fmaxnm z0.h, p0/m, z0.h, #0.9999999999999999999999999 label
35 fmaxnm z0.h, p7/m, z1.h, z31.h label
44 fmaxnm z0.b, p7/m, z0.b, z31.b label
49 fmaxnm z0.h, p7/m, z0.h, z31.s label
58 fmaxnm z0.h, p8/m, z0.h, z31.h label
/external/llvm/test/CodeGen/AArch64/
Darm64-vminmaxnm.ll4 ; CHECK: fmaxnm.2s v0, v0, v1
6 …%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b)…
11 ; CHECK: fmaxnm.4s v0, v0, v1
13 …%vmaxnm2.i = tail call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b)…
18 ; CHECK: fmaxnm.2d v0, v0, v1
20 …%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> …
46 ; CHECK: fmaxnm s0, s0, s1
48 %vmaxnm2.i = tail call float @llvm.aarch64.neon.fmaxnm.f32(float %a, float %b) nounwind
62 declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
[all …]
Darm64-neon-add-sub.ll205 ; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
233 declare <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double>, <1 x double>)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vminmaxnm.ll4 ; CHECK: fmaxnm.2s v0, v0, v1
6 …%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b)…
11 ; CHECK: fmaxnm.4s v0, v0, v1
13 …%vmaxnm2.i = tail call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b)…
18 ; CHECK: fmaxnm.2d v0, v0, v1
20 …%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> …
46 ; CHECK: fmaxnm s0, s0, s1
48 %vmaxnm2.i = tail call float @llvm.aarch64.neon.fmaxnm.f32(float %a, float %b) nounwind
62 declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
63 declare <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
[all …]
Darm64-neon-add-sub.ll205 ; CHECK: fmaxnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
206 %1 = tail call <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double> %a, <1 x double> %b)
233 declare <1 x double> @llvm.aarch64.neon.fmaxnm.v1f64(<1 x double>, <1 x double>)
Df16-instructions.ll957 ; CHECK-CVT-NEXT: fmaxnm s0, s0, s1
962 ; CHECK-FP16-NEXT: fmaxnm h0, h0, h1
/external/llvm/test/MC/AArch64/
Dneon-max-min.s100 fmaxnm v0.4h, v1.4h, v2.4h
101 fmaxnm v0.8h, v1.8h, v2.8h
102 fmaxnm v0.2s, v1.2s, v2.2s
103 fmaxnm v31.4s, v15.4s, v16.4s
104 fmaxnm v7.2d, v8.2d, v25.2d
Darm64-fp-encoding.s53 fmaxnm h1, h2, h3
54 fmaxnm s1, s2, s3
55 fmaxnm d1, d2, d3 define
62 ; FP16: fmaxnm h1, h2, h3 ; encoding: [0x41,0x68,0xe3,0x1e]
64 ; NO-FP16-NEXT: fmaxnm h1, h2, h3
65 ; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
66 ; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
Dfullfp16-neon-neg.s200 fmaxnm v0.4h, v1.4h, v2.4h
202 fmaxnm v0.8h, v1.8h, v2.8h
Darm64-advsimd.s318 fmaxnm.2s v0, v0, v0
388 ; CHECK: fmaxnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x0e]
453 fmaxnm.4h v0, v0, v0
478 ; CHECK: fmaxnm.4h v0, v0, v0 ; encoding: [0x00,0x04,0x40,0x0e]
503 fmaxnm.8h v0, v0, v0
528 ; CHECK: fmaxnm.8h v0, v0, v0 ; encoding: [0x00,0x04,0x40,0x4e]
Dbasic-a64-diagnostics.s1632 fmaxnm d3, s19, d12 define
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-max-min.s100 fmaxnm v0.4h, v1.4h, v2.4h
101 fmaxnm v0.8h, v1.8h, v2.8h
102 fmaxnm v0.2s, v1.2s, v2.2s
103 fmaxnm v31.4s, v15.4s, v16.4s
104 fmaxnm v7.2d, v8.2d, v25.2d
Darm64-fp-encoding.s53 fmaxnm h1, h2, h3
54 fmaxnm s1, s2, s3
55 fmaxnm d1, d2, d3 define
62 ; FP16: fmaxnm h1, h2, h3 ; encoding: [0x41,0x68,0xe3,0x1e]
64 ; NO-FP16-NEXT: fmaxnm h1, h2, h3
65 ; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
66 ; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
Dfullfp16-neon-neg.s200 fmaxnm v0.4h, v1.4h, v2.4h
202 fmaxnm v0.8h, v1.8h, v2.8h
Darm64-advsimd.s318 fmaxnm.2s v0, v0, v0
388 ; CHECK: fmaxnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x0e]
453 fmaxnm.4h v0, v0, v0
478 ; CHECK: fmaxnm.4h v0, v0, v0 ; encoding: [0x00,0x04,0x40,0x0e]
503 fmaxnm.8h v0, v0, v0
528 ; CHECK: fmaxnm.8h v0, v0, v0 ; encoding: [0x00,0x04,0x40,0x4e]
Dbasic-a64-diagnostics.s1637 fmaxnm d3, s19, d12 define
/external/capstone/suite/MC/AArch64/
Dneon-max-min.s.cs32 0x20,0xc4,0x22,0x0e = fmaxnm v0.2s, v1.2s, v2.2s
33 0xff,0xc5,0x30,0x4e = fmaxnm v31.4s, v15.4s, v16.4s
34 0x07,0xc5,0x79,0x4e = fmaxnm v7.2d, v8.2d, v25.2d
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt50 # FP16: fmaxnm h1, h2, h3
51 # CHECK: fmaxnm s1, s2, s3
52 # CHECK: fmaxnm d1, d2, d3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt50 # FP16: fmaxnm h1, h2, h3
51 # CHECK: fmaxnm s1, s2, s3
52 # CHECK: fmaxnm d1, d2, d3
/external/vixl/doc/
Dchangelog.md98 + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,
/external/v8/src/arm64/
Dsimulator-arm64.h1884 V(fmaxnm, FPMaxNM, false) \
1899 V(fmaxnmp, fmaxnm, FPMaxNM) \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td123 defm FMAXNM_ZPmI : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>;
132 defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm">;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc11847 "fjcvtzs\004fmad\005fmadd\004fmax\006fmaxnm\007fmaxnmp\007fmaxnmv\005fma"
13327 …{ 1245 /* fmaxnm */, AArch64::FMAXNMHrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFullFP16, { M…
13328 …{ 1245 /* fmaxnm */, AArch64::FMAXNMSrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MC…
13329 …{ 1245 /* fmaxnm */, AArch64::FMAXNMDrr, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasFPARMv8, { MC…
13330 …{ 1245 /* fmaxnm */, AArch64::FMAXNMv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg128…
13331 …{ 1245 /* fmaxnm */, AArch64::FMAXNMv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg128…
13332 …{ 1245 /* fmaxnm */, AArch64::FMAXNMv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg128…
13333 …{ 1245 /* fmaxnm */, AArch64::FMAXNMv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4…
13334 …{ 1245 /* fmaxnm */, AArch64::FMAXNMv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4…
13335 …{ 1245 /* fmaxnm */, AArch64::FMAXNM_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__T…
[all …]
/external/vixl/test/aarch64/
Dtest-cpu-features-aarch64.cc607 TEST_FP(fmaxnm_0, fmaxnm(d0, d1, d2))
608 TEST_FP(fmaxnm_1, fmaxnm(s0, s1, s2))
3206 TEST_FP_NEON(fmaxnm_0, fmaxnm(v0.V2S(), v1.V2S(), v2.V2S()))
3207 TEST_FP_NEON(fmaxnm_1, fmaxnm(v0.V4S(), v1.V4S(), v2.V4S()))
3208 TEST_FP_NEON(fmaxnm_2, fmaxnm(v0.V2D(), v1.V2D(), v2.V2D()))
3418 TEST_FP_FPHALF(fmaxnm_0, fmaxnm(h0, h1, h2))
3577 TEST_FP_NEON_NEONHALF(fmaxnm_0, fmaxnm(v0.V4H(), v1.V4H(), v2.V4H()))
3578 TEST_FP_NEON_NEONHALF(fmaxnm_1, fmaxnm(v0.V8H(), v1.V8H(), v2.V8H()))

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