Searched refs:fmaxnmv (Results 1 – 25 of 51) sorted by relevance
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3 fmaxnmv b0, p7, z31.b label8 fmaxnmv h0, p8, z31.h label17 fmaxnmv v0, p7, z31.h label26 fmaxnmv d0, p7, z31.d define32 fmaxnmv d0, p7, z31.d define
10 fmaxnmv h0, p7, z31.h label16 fmaxnmv s0, p7, z31.s label22 fmaxnmv d0, p7, z31.d define
81 %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)87 ; CHECK: fmaxnmv s0, v0.4s88 %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)95 %maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)99 declare float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float>)100 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)101 declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>)
71 %max = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)82 declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>)
5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)447 ; CHECK: fmaxnmv s{{[0-9]+}}, {{v[0-9]+}}.4s449 %0 = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %a)
290 ; CHECK: fmaxnmv
119 ; CHECK: fmaxnmv
93 fmaxnmv h0, v1.4h97 fmaxnmv h0, v1.8h101 fmaxnmv s0, v1.4s
72 fmaxnmv h0, v1.8h
3817 fmaxnmv b0, v1.16b3835 fmaxnmv h0, v1.8h3853 fmaxnmv d0, v1.2d define
3757 fmaxnmv b0, v1.16b3775 fmaxnmv h0, v1.8h3793 fmaxnmv d0, v1.2d define
37 0x20,0xc8,0x30,0x6e = fmaxnmv s0, v1.4s
241 ; CODE: fmaxnmv s0, v0.4s
300 V(fmaxnmv, Fmaxnmv) \
2009 LogicVRegister fmaxnmv(VectorFormat vform, LogicVRegister dst,
1991 void fmaxnmv(const VRegister& vd, const VRegister& vn);
175 defm FMAXNMV_VPZ : sve_fp_fast_red<0b100, "fmaxnmv">;
4691 fmaxnmv(vf, rd, rn); in VisitNEONAcrossLanes()4711 fmaxnmv(vf, rd, rn); in VisitNEONAcrossLanes()
2991 LogicVRegister fmaxnmv(VectorFormat vform,
11847 "fjcvtzs\004fmad\005fmadd\004fmax\006fmaxnm\007fmaxnmp\007fmaxnmv\005fma"13349 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorH…13350 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Fe…13351 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Fea…13352 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorS…13353 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, {…13354 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorD…19818 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv4i16v, Convert__Reg1_1__VectorReg641_2, Feature_HasNEON|Fea…19819 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv4i32v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON, {…19820 …{ 1260 /* fmaxnmv */, AArch64::FMAXNMVv8i16v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON|Fe…[all …]