Searched refs:fmaxv (Results 1 – 25 of 48) sorted by relevance
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3 fmaxv b0, p7, z31.b label8 fmaxv h0, p8, z31.h label17 fmaxv v0, p7, z31.h label26 fmaxv d0, p7, z31.d define32 fmaxv d0, p7, z31.d define
10 fmaxv h0, p7, z31.h label16 fmaxv s0, p7, z31.s label22 fmaxv d0, p7, z31.d define
31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)37 ; CHECK: fmaxv s0, v0.4s38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in)49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)50 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)51 declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)
9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)431 ; CHECK: fmaxv s{{[0-9]+}}, {{v[0-9]+}}.4s433 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a)
1069 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1081 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1088 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
1072 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1084 %0 = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %a)1091 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)
95 fmaxv h0, v1.4h99 fmaxv h0, v1.8h103 fmaxv s0, v1.4s
76 fmaxv h0, v1.8h
3819 fmaxv b0, v1.16b3837 fmaxv h0, v1.8h3855 fmaxv d0, v1.2d define
3759 fmaxv b0, v1.16b3777 fmaxv h0, v1.8h3795 fmaxv d0, v1.2d define
39 0x20,0xf8,0x30,0x6e = fmaxv s0, v1.4s
302 V(fmaxv, Fmaxv) \
2005 LogicVRegister fmaxv(VectorFormat vform, LogicVRegister dst,
1994 void fmaxv(const VRegister& vd, const VRegister& vn);
177 defm FMAXV_VPZ : sve_fp_fast_red<0b110, "fmaxv">;
4685 fmaxv(vf, rd, rn); in VisitNEONAcrossLanes()4705 fmaxv(vf, rd, rn); in VisitNEONAcrossLanes()
2985 LogicVRegister fmaxv(VectorFormat vform,
2968 void fmaxv(const VRegister& vd, const VRegister& vn);
2694 V(fmaxv, Fmaxv) \
11848 "xp\005fmaxv\004fmin\006fminnm\007fminnmp\007fminnmv\005fminp\005fminv\004"13363 …{ 1274 /* fmaxv */, AArch64::FMAXV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…13364 …{ 1274 /* fmaxv */, AArch64::FMAXVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Featur…13365 …{ 1274 /* fmaxv */, AArch64::FMAXVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature…13366 …{ 1274 /* fmaxv */, AArch64::FMAXV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…13367 …{ 1274 /* fmaxv */, AArch64::FMAXVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK…13368 …{ 1274 /* fmaxv */, AArch64::FMAXV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…19832 …{ 1274 /* fmaxv */, AArch64::FMAXVv4i16v, Convert__Reg1_1__VectorReg641_2, Feature_HasNEON|Feature…19833 …{ 1274 /* fmaxv */, AArch64::FMAXVv4i32v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON, { MCK…19834 …{ 1274 /* fmaxv */, AArch64::FMAXVv8i16v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON|Featur…[all …]
2076 void fmaxv(const VRegister& vd, const VRegister& vn)