Searched refs:fminv (Results 1 – 25 of 46) sorted by relevance
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3 fminv b0, p7, z31.b label8 fminv h0, p8, z31.h label17 fminv v0, p7, z31.h label26 fminv d0, p7, z31.d define32 fminv d0, p7, z31.d define
10 fminv h0, p7, z31.h label16 fminv s0, p7, z31.s label22 fminv d0, p7, z31.d define
6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)12 ; CHECK: fminv s0, v0.4s13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)
7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)439 ; CHECK: fminv s{{[0-9]+}}, {{v[0-9]+}}.4s441 %0 = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a)
96 fminv h0, v1.4h100 fminv h0, v1.8h104 fminv s0, v1.4s
78 fminv h0, v1.8h
3820 fminv b0, v1.16b3838 fminv h0, v1.8h3856 fminv d0, v1.2d define
3760 fminv b0, v1.16b3778 fminv h0, v1.8h3796 fminv d0, v1.2d define
40 0x20,0xf8,0xb0,0x6e = fminv s0, v1.4s
306 V(fminv, Fminv) \
2003 LogicVRegister fminv(VectorFormat vform, LogicVRegister dst,
2000 void fminv(const VRegister& vd, const VRegister& vn);
4158 fminv(vf, rd, rn); in VisitNEONAcrossLanes()
178 defm FMINV_VPZ : sve_fp_fast_red<0b111, "fminv">;
4688 fminv(vf, rd, rn); in VisitNEONAcrossLanes()4708 fminv(vf, rd, rn); in VisitNEONAcrossLanes()
2982 LogicVRegister fminv(VectorFormat vform,
2974 void fminv(const VRegister& vd, const VRegister& vn);
2698 V(fminv, Fminv) \
11848 "xp\005fmaxv\004fmin\006fminnm\007fminnmp\007fminnmv\005fminp\005fminv\004"13419 …{ 1314 /* fminv */, AArch64::FMINV_VPZ_H, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorHReg1…13420 …{ 1314 /* fminv */, AArch64::FMINVv8i16v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON|Featur…13421 …{ 1314 /* fminv */, AArch64::FMINVv4i16v, Convert__Reg1_0__VectorReg641_1, Feature_HasNEON|Feature…13422 …{ 1314 /* fminv */, AArch64::FMINV_VPZ_S, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1…13423 …{ 1314 /* fminv */, AArch64::FMINVv4i32v, Convert__Reg1_0__VectorReg1281_1, Feature_HasNEON, { MCK…13424 …{ 1314 /* fminv */, AArch64::FMINV_VPZ_D, Convert__Reg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1…19888 …{ 1314 /* fminv */, AArch64::FMINVv4i16v, Convert__Reg1_1__VectorReg641_2, Feature_HasNEON|Feature…19889 …{ 1314 /* fminv */, AArch64::FMINVv4i32v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON, { MCK…19890 …{ 1314 /* fminv */, AArch64::FMINVv8i16v, Convert__Reg1_1__VectorReg1281_2, Feature_HasNEON|Featur…[all …]
2132 void fminv(const VRegister& vd, const VRegister& vn)
4863 DEFINE_TEST_NEON_ACROSS_FP(fminv, Basic) in DEFINE_TEST_NEON_2SAME_FP_FP16_SCALAR()