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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Ddefault-fp-mode.ll112 attributes #2 = { nounwind "target-features"="+fp64-denormals" }
114 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
115 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-fp16-denormals" }
116 attributes #6 = { nounwind "target-features"="+fp64-fp16-denormals" }
117 attributes #7 = { nounwind "target-features"="-fp64-fp16-denormals" }
118 attributes #8 = { nounwind "target-features"="+fp32-denormals,+fp64-fp16-denormals" }
Dfmuladd.v2f16.ll1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-deno…
2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-deno…
3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-deno…
4 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-fp64-fp16-deno…
6 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-deno…
7 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-deno…
8 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-deno…
9 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=+fp64-fp16-deno…
Dhsa-fp-mode.ll75 attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-fp16-denormals" }
76 attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-fp16-denormals" }
77 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-fp16-denormals" }
78 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-fp16-denormals" }
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dfp64a.ll14 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-F…
15 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=AL…
16 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO…
17 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=…
19 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP6…
20 ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-pr…
21 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-F…
22 ; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-…
Dfp-contract.ll4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s --check-prefixes=CHECK-CONTRACT-OFF
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -fp-contract=off < %s | FileCheck %s --check-prefixes=CH…
6 ; RUN: llc -march=mips -mattr=+msa,+fp64 -fp-contract=fast < %s | FileCheck %s --check-prefixes=CHE…
D2013-11-18-fp64-const0.ll1 ; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s
2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
/external/llvm/test/CodeGen/Mips/
Dfp64a.ll14 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-F…
15 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=AL…
16 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO…
17 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=…
19 ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP6…
20 ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-pr…
21 ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-F…
22 ; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-…
D2013-11-18-fp64-const0.ll1 ; RUN: llc -march=mips -mattr=-fp64 < %s | FileCheck -check-prefix=CHECK-FP32 %s
2 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=CHECK-FP64 %s
/external/llvm/test/CodeGen/AMDGPU/
Dhsa-fp-mode.ll65 attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-denormals" }
66 attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-denormals" }
67 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
68 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
Ddefault-fp-mode.ll59 attributes #2 = { nounwind "target-features"="+fp64-denormals" }
61 attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
62 attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" }
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
Doddspreg.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
24 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \
5 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - …
9 # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - …
Dmicromips-fpu64-instructions.s1 # RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips,fp64 \
3 # RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips,fp64 \
/external/mesa3d/src/compiler/glsl/
Dbuiltin_functions.cpp576 fp64(const _mesa_glsl_parse_state *state) in fp64() function
1289 _##NAME(fp64, glsl_type::double_type), \ in create_builtins()
1290 _##NAME(fp64, glsl_type::dvec2_type), \ in create_builtins()
1291 _##NAME(fp64, glsl_type::dvec3_type), \ in create_builtins()
1292 _##NAME(fp64, glsl_type::dvec4_type), \ in create_builtins()
1301 _##NAME(fp64, glsl_type::double_type), \ in create_builtins()
1302 _##NAME(fp64, glsl_type::dvec2_type), \ in create_builtins()
1303 _##NAME(fp64, glsl_type::dvec3_type), \ in create_builtins()
1304 _##NAME(fp64, glsl_type::dvec4_type), \ in create_builtins()
1313 _##NAME(fp64, glsl_type::double_type), \ in create_builtins()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
D2r_vector_scalar.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
Dllvm-stress-sz1-s742806235.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
Delm_move.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
Dllvm-stress-s2501752154-simplified.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
/external/llvm/test/CodeGen/Mips/msa/
D2r_vector_scalar.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \
Dllvm-stress-sz1-s742806235.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
Delm_move.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
Dllvm-stress-s2501752154-simplified.ll2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-fpxx1.ll1 ; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
2 ; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-fpxx1.ll1 ; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s
2 ; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=O32-FP64-INV %s

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