| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-fpcr.ll | 7 %1 = tail call i64 @llvm.aarch64.get.fpcr()
11 declare i64 @llvm.aarch64.get.fpcr() #0
|
| /external/google-breakpad/src/client/linux/dump_writer_common/ |
| D | thread_info.cc | 202 (static_cast<uint64_t>(fpregs.fpcr) << 32);
225 out->float_save.fpcr = fpregs.fpcr;
|
| D | ucontext_reader.cc | 206 out->float_save.fpcr = fpregs->fpcr;
|
| /external/google-breakpad/src/google_breakpad/common/ |
| D | minidump_cpu_arm64.h | 73 uint32_t fpcr; /* FPU control register */ member
|
| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| D | sigcontext.h | 76 __u32 fpcr; member
|
| D | ptrace.h | 83 __u32 fpcr; member
|
| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 1344 DCHECK(fpcr().RMode() < arraysize(rmode)); in PrintSystemRegister()
1348 fpcr().AHP(), fpcr().DN(), fpcr().FZ(), rmode[fpcr().RMode()], in PrintSystemRegister()
2541 FPRounding round = fpcr().RMode(); in VisitFPIntegerConvert()
2626 FPRounding round = fpcr().RMode(); in VisitFPFixedPointConvert()
2733 FPRounding fpcr_rounding = static_cast<FPRounding>(fpcr().RMode()); in VisitFPDataProcessing1Source()
2947 case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break; in VisitSystem()
2959 fpcr().SetRawValue(wreg(instr->Rt())); in VisitSystem()
3553 FPRounding fpcr_rounding = static_cast<FPRounding>(fpcr().RMode()); in VisitNEON2RegMisc()
4918 FPRounding fpcr_rounding = static_cast<FPRounding>(fpcr().RMode()); in VisitNEONScalar2RegMisc()
5255 FPRounding fpcr_rounding = static_cast<FPRounding>(fpcr().RMode()); in VisitNEONScalarShiftImmediate()
[all …]
|
| D | macro-assembler-arm64.cc | 1485 void TurboAssembler::AssertFPCRState(Register fpcr) { in AssertFPCRState() argument
1489 if (fpcr.IsNone()) { in AssertFPCRState()
1490 fpcr = temps.AcquireX(); in AssertFPCRState()
1491 Mrs(fpcr, FPCR); in AssertFPCRState()
1496 Tbnz(fpcr, FZ_offset, &unexpected_mode); in AssertFPCRState()
1499 Tst(fpcr, RMode_mask); in AssertFPCRState()
|
| D | simulator-arm64.h | 1027 SimSystemRegister& fpcr() { return fpcr_; } in fpcr() function
2141 DCHECK_EQ(fpcr().FZ(), 0); // No flush-to-zero support. in AssertSupportedFPCR()
2142 DCHECK(fpcr().RMode() == FPTieEven); // Ties-to-even rounding only. in AssertSupportedFPCR()
2303 return fpcr().DN() ? FPDefaultNaN<T>() : ToQuietNaN(op); in FPProcessNaN()
|
| D | macro-assembler-arm64.h | 995 void AssertFPCRState(Register fpcr = NoReg);
|
| /external/google-breakpad/src/common/android/ |
| D | breakpad_getcontext.S | 153 mrs x4, fpcr
|
| /external/google-breakpad/src/processor/ |
| D | dump_context.cc | 549 printf(" float_save.fpcr = 0x%x\n", context_arm64->float_save.fpcr); in Print()
|
| D | minidump.cc | 706 Swap(&context_arm64->float_save.fpcr); in Read()
|
| /external/elfutils/tests/ |
| D | run-readelf-mixed-corenote.sh | 356 fpsr: 0x00000000, fpcr: 0x00000000
|
| D | run-allregs.sh | 2585 63: $fpcr (fpcr), unsigned 64 bits
|
| /external/python/cpython3/ |
| D | configure.ac | 4443 AC_MSG_CHECKING(whether we can use gcc inline assembler to get and set mc68881 fpcr)
4445 unsigned int fpcr;
4446 __asm__ __volatile__ ("fmove.l %%fpcr,%0" : "=g" (fpcr));
4447 __asm__ __volatile__ ("fmove.l %0,%%fpcr" : : "g" (fpcr));
4453 [Define if we can use gcc inline assembler to get and set mc68881 fpcr])
|
| D | pyconfig.h.in | 387 /* Define if we can use gcc inline assembler to get and set mc68881 fpcr */
|
| D | configure | 14430 unsigned int fpcr;
14431 __asm__ __volatile__ ("fmove.l %%fpcr,%0" : "=g" (fpcr));
14432 __asm__ __volatile__ ("fmove.l %0,%%fpcr" : : "g" (fpcr));
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 1574 0x0c,0x44,0x1b,0xd5 = msr fpcr, x12
1886 0x09,0x44,0x3b,0xd5 = mrs x9, fpcr
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 1304 VIXL_DEPRECATED("ReadFpcr", SimSystemRegister& fpcr()) { return ReadFpcr(); }
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3300 # CHECK: msr {{fpcr|FPCR}}, x12
3592 # CHECK: mrs x9, {{fpcr|FPCR}}
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 3284 # CHECK: msr {{fpcr|FPCR}}, x12
3577 # CHECK: mrs x9, {{fpcr|FPCR}}
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 224 aarch64_get_fpcr, // llvm.aarch64.get.fpcr
|
| D | IntrinsicImpl.inc | 250 "llvm.aarch64.get.fpcr",
9128 1, // llvm.aarch64.get.fpcr
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/transforms/ |
| D | internal_raw_IPA-old.txt | 74004 fpcr %17553
|