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Searched refs:fpga (Results 1 – 25 of 43) sorted by relevance

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/external/u-boot/board/gdsys/common/
Dcmd_ioloop.c55 static void io_check_status(unsigned int fpga, u16 status, bool silent) in io_check_status() argument
62 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
67 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
88 static void io_send(unsigned int fpga, unsigned int size) in io_send() argument
99 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
102 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
104 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
110 static void io_receive(unsigned int fpga) in io_receive() argument
115 FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); in io_receive()
123 FPGA_GET_REG(fpga, ep.receive_data, &rx); in io_receive()
[all …]
Dihs_mdio.c26 static inline u16 read_reg(struct udevice *fpga, uint base, uint addr) in read_reg() argument
31 regmap_init_mem(fpga, &map); in read_reg()
37 static inline void write_reg(struct udevice *fpga, uint base, uint addr, in write_reg() argument
43 regmap_init_mem(fpga, &map); in write_reg()
54 FPGA_GET_REG(info->fpga, mdio.control, &val); in read_control()
56 val = read_reg(info->fpga, info->base, REG_MDIO_CONTROL); in read_control()
64 FPGA_SET_REG(info->fpga, mdio.control, val); in write_control()
66 write_reg(info->fpga, info->base, REG_MDIO_CONTROL, val); in write_control()
73 FPGA_SET_REG(info->fpga, mdio.address_data, val); in write_addr_data()
75 write_reg(info->fpga, info->base, REG_MDIO_ADDR_DATA, val); in write_addr_data()
[all …]
Dioep-fpga.c54 bool ioep_fpga_has_osd(unsigned int fpga) in ioep_fpga_has_osd() argument
65 void ioep_fpga_print_info(unsigned int fpga) in ioep_fpga_print_info() argument
81 FPGA_GET_REG(fpga, versions, &versions); in ioep_fpga_print_info()
82 FPGA_GET_REG(fpga, fpga_version, &fpga_version); in ioep_fpga_print_info()
83 FPGA_GET_REG(fpga, fpga_features, &fpga_features); in ioep_fpga_print_info()
DMakefile6 obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
13 obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
14 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
Dioep-fpga.h10 void ioep_fpga_print_info(unsigned int fpga);
11 bool ioep_fpga_has_osd(unsigned int fpga);
Dihs_mdio.h12 u32 fpga; member
14 struct udevice *fpga;
Dfpga.c12 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
19 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
/external/u-boot/drivers/fpga/
Daltera.c99 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); in altera_load() local
101 if (!fpga) in altera_load()
105 __func__, fpga->name); in altera_load()
106 if (fpga->load) in altera_load()
107 return fpga->load(desc, buf, bsize); in altera_load()
113 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__); in altera_dump() local
115 if (!fpga) in altera_dump()
119 __func__, fpga->name); in altera_dump()
120 if (fpga->dump) in altera_dump()
121 return fpga->dump(desc, buf, bsize); in altera_dump()
[all …]
DKconfig14 (in BIT format), fpga and device validation.
39 (in BIT format), fpga and device validation.
/external/u-boot/board/gdsys/a38x/
Dhydra.c18 static struct ihs_fpga *fpga; variable
22 return fpga; in get_fpga()
27 u32 versions = readl(&fpga->versions); in print_hydra_version()
28 u32 fpga_version = readl(&fpga->fpga_version); in print_hydra_version()
32 printf("FPGA%u: mapped to %p\n ", index, fpga); in print_hydra_version()
82 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in hydra_initialize()
98 if (!fpga) in do_hydrate()
104 writel(REFL_PATTERN, &fpga->reflection_low); in do_hydrate()
105 res = readl(&fpga->reflection_low); in do_hydrate()
109 writel(REFL_PATTERN_INV, &fpga->reflection_low); in do_hydrate()
[all …]
/external/u-boot/board/gdsys/mpc8308/
Dstrider.c61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
65 switch (fpga) { in fpga_set_reg()
70 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
82 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
86 switch (fpga) { in fpga_get_reg()
91 if (fpga > mclink_fpgacount) in fpga_get_reg()
93 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
347 int mpc8308_get_fpga_done(unsigned fpga) in mpc8308_get_fpga_done() argument
425 unsigned fpga; member
444 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
[all …]
Dhrcon.c58 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
62 switch (fpga) { in fpga_set_reg()
67 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
79 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
83 switch (fpga) { in fpga_get_reg()
88 if (fpga > mclink_fpgacount) in fpga_get_reg()
90 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
292 int mpc8308_get_fpga_done(unsigned fpga) in mpc8308_get_fpga_done() argument
370 unsigned fpga; member
389 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
[all …]
Dmpc8308.h8 int mpc8308_get_fpga_done(unsigned fpga);
/external/u-boot/cmd/
Dfpgad.c31 unsigned int fpga; in do_fpga_md() local
41 fpga = dp_last_fpga; in do_fpga_md()
52 fpga = simple_strtoul(argv[1], NULL, 16); in do_fpga_md()
73 fpga_get_reg(fpga, in do_fpga_md()
74 (u16 *)fpga_ptr[fpga] + addr in do_fpga_md()
90 dp_last_fpga = fpga; in do_fpga_md()
/external/u-boot/doc/uImage.FIT/
Dmulti-with-fpga.its9 description = "Configuration to load fpga before Kernel";
25 fpga {
28 type = "fpga";
61 description = "Linux with fpga";
64 fpga = "fpga";
/external/u-boot/drivers/i2c/
Dihs_i2c.c95 struct udevice *fpga; in wait_for_int() local
97 gdsys_soc_get_fpga(dev, &fpga); in wait_for_int()
101 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, in wait_for_int()
113 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, in wait_for_int()
135 struct udevice *fpga; in ihs_i2c_transfer() local
137 gdsys_soc_get_fpga(dev, &fpga); in ihs_i2c_transfer()
143 fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data, in ihs_i2c_transfer()
145 fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val, in ihs_i2c_transfer()
159 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val, in ihs_i2c_transfer()
173 fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data, in ihs_i2c_transfer()
[all …]
/external/u-boot/arch/arm/mach-zynq/
Dcpu.c19 xilinx_desc fpga = { variable
118 fpga.size = zynq_fpga_descs[cpu_id].fpga_size; in arch_early_init_r()
119 fpga.name = zynq_fpga_descs[cpu_id].devicename; in arch_early_init_r()
121 fpga_add(fpga_xilinx, &fpga); in arch_early_init_r()
/external/u-boot/board/gdsys/p1022/
Dcontrolcenterd.c359 struct ihs_fpga *fpga; in hydra_initialize() local
384 fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in hydra_initialize()
388 writel(1, &fpga->control); in hydra_initialize()
390 versions = readl(&fpga->versions); in hydra_initialize()
391 fpga_version = readl(&fpga->fpga_version); in hydra_initialize()
392 fpga_features = readl(&fpga->fpga_features); in hydra_initialize()
/external/u-boot/doc/device-tree-bindings/fpga/
Daltera-socfpga-a10-fpga-mgr.txt4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
/external/u-boot/arch/arm/dts/
Dfsl-ls1088a-qds.dts46 fpga: board-control@3,0 { label
49 compatible = "simple-bus", "fsl,ls1088aqds-fpga",
50 "fsl,fpga-qixis";
/external/u-boot/board/spear/x600/
Dfpga.c175 static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
260 fpga_add(fpga_xilinx, &fpga[0]); in x600_init_fpga()
/external/u-boot/board/armadeus/apf27/
Dfpga.c44 xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
220 fpga_add(fpga_xilinx, &fpga[i]); in APF27_init_fpga()
/external/u-boot/drivers/
DMakefile52 obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
76 obj-$(CONFIG_FPGA) += fpga/
/external/u-boot/board/astro/mcf5373l/
DMakefile6 obj-y = mcf5373l.o fpga.o
/external/u-boot/board/theadorable/
DMakefile6 obj-y += fpga.o

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