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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-with-no-legality-check.mir12 - { id: 0, class: fpr }
13 - { id: 1, class: fpr }
26 %1:fpr(p0) = COPY $d0
27 %0:fpr(s128) = G_LOAD %1(p0) :: (load 16)
38 - { id: 0, class: fpr }
39 - { id: 1, class: fpr }
54 %1:fpr(p0) = COPY $d1
55 %0:fpr(<8 x s8>) = COPY $d0
67 - { id: 0, class: fpr }
68 - { id: 1, class: fpr }
[all …]
Dlocalizer-in-O0-pipeline.mir38 # CHECK-NEXT: - { id: 0, class: fpr, preferred-register: '' }
40 # CHECK-NEXT: - { id: 2, class: fpr, preferred-register: '' }
41 # CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
42 # CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
43 # CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
46 # OPTNONE-NEXT: - { id: 7, class: fpr, preferred-register: '' }
47 # OPTNONE-NEXT: - { id: 8, class: fpr, preferred-register: '' }
48 - { id: 0, class: fpr }
50 - { id: 2, class: fpr }
51 - { id: 3, class: fpr }
[all …]
Dlocalizer.mir203 ; CHECK: [[C:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
204 ; CHECK: [[FADD:%[0-9]+]]:fpr(s32) = G_FADD [[C]], [[C]]
207 ; CHECK: [[C1:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
209 ; CHECK: [[PHI:%[0-9]+]]:fpr(s32) = PHI [[C1]](s32), %bb.1
210 ; CHECK: [[C2:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
211 ; CHECK: [[FADD1:%[0-9]+]]:fpr(s32) = G_FADD [[PHI]], [[C2]]
219 %0:fpr(s32) = G_FCONSTANT float 1.0
220 %1:fpr(s32) = G_FADD %0, %0
226 %3:fpr(s32) = PHI %0(s32), %bb.1
227 %2:fpr(s32) = G_FADD %3, %0
[all …]
Darm64-regbankselect.mir134 # Based on the type <2 x i32>, this should be fpr.
145 ; CHECK: %0:fpr(<2 x s32>) = COPY $d0
146 ; CHECK: %1:fpr(<2 x s32>) = G_ADD %0
165 ; CHECK: %0:fpr(s32) = COPY $s0
184 ; CHECK: %0:fpr(s32) = COPY $s0
201 - { id: 1, class: fpr }
208 ; CHECK-NEXT: %1:fpr(s32) = COPY %2
265 ; CHECK-NEXT: %1:fpr(s32) = COPY $s0
294 # G_OR instruction from fpr to gpr.
310 ; FAST-NEXT: %3:fpr(<2 x s32>) = COPY %0
[all …]
Dselect-fp-casts.mir42 - { id: 0, class: fpr }
43 - { id: 1, class: fpr }
64 - { id: 0, class: fpr }
65 - { id: 1, class: fpr }
86 - { id: 0, class: fpr }
87 - { id: 1, class: fpr }
108 - { id: 0, class: fpr }
109 - { id: 1, class: fpr }
130 - { id: 0, class: fpr }
131 - { id: 1, class: fpr }
[all …]
Dselect-bitcast.mir45 - { id: 0, class: fpr }
46 - { id: 1, class: fpr }
67 - { id: 1, class: fpr }
88 - { id: 0, class: fpr }
131 - { id: 0, class: fpr }
132 - { id: 1, class: fpr }
153 - { id: 1, class: fpr }
173 - { id: 0, class: fpr }
195 - { id: 0, class: fpr }
196 - { id: 1, class: fpr }
[all …]
Dregbankselect-default.mir101 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
102 ; CHECK: [[ADD:%[0-9]+]]:fpr(<4 x s32>) = G_ADD [[COPY]], [[COPY]]
133 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
134 ; CHECK: [[SUB:%[0-9]+]]:fpr(<4 x s32>) = G_SUB [[COPY]], [[COPY]]
165 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
166 ; CHECK: [[MUL:%[0-9]+]]:fpr(<4 x s32>) = G_MUL [[COPY]], [[COPY]]
197 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
198 ; CHECK: [[AND:%[0-9]+]]:fpr(<4 x s32>) = G_AND [[COPY]], [[COPY]]
229 ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
230 ; CHECK: [[OR:%[0-9]+]]:fpr(<4 x s32>) = G_OR [[COPY]], [[COPY]]
[all …]
Dselect-binop.mir303 - { id: 0, class: fpr }
304 - { id: 1, class: fpr }
305 - { id: 2, class: fpr }
722 - { id: 0, class: fpr }
723 - { id: 1, class: fpr }
724 - { id: 2, class: fpr }
747 - { id: 0, class: fpr }
748 - { id: 1, class: fpr }
749 - { id: 2, class: fpr }
772 - { id: 0, class: fpr }
[all …]
Dselect-fma.mir16 - { id: 0, class: fpr }
17 - { id: 1, class: fpr }
18 - { id: 2, class: fpr }
19 - { id: 3, class: fpr }
Dselect-intrinsic-crypto-aesmc.mir21 %0:fpr(<16 x s8>) = COPY $q0
22 %1:fpr(<16 x s8>) = COPY $q1
23 %2:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aese), %0, %1
24 %3:fpr(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.aarch64.crypto.aesmc), %2
Dfp16-copy-gpr.mir30 - { id: 1, class: fpr }
31 - { id: 2, class: fpr }
60 %1:fpr(s16) = COPY $h0
61 %2:fpr(s16) = COPY $h1
83 - { id: 2, class: fpr }
97 %2:fpr(s16) = COPY %1(s16)
Dselect-constant.mir53 - { id: 0, class: fpr }
70 - { id: 0, class: fpr }
87 - { id: 0, class: fpr }
103 - { id: 0, class: fpr }
Dselect-load.mir304 - { id: 1, class: fpr }
326 - { id: 1, class: fpr }
348 - { id: 1, class: fpr }
370 - { id: 1, class: fpr }
394 - { id: 3, class: fpr }
420 - { id: 3, class: fpr }
446 - { id: 3, class: fpr }
472 - { id: 3, class: fpr }
495 - { id: 1, class: fpr }
Dselect-bitcast-bigendian.mir15 %0:fpr(<2 x s32>) = COPY $x0
16 %1:fpr(s64) = G_BITCAST %0
Dselect-neon-vcvtfxu2fp.mir17 - { id: 0, class: fpr }
19 - { id: 2, class: fpr }
/external/linux-kselftest/tools/testing/selftests/powerpc/ptrace/
Dptrace-gpr.h43 int validate_fpr(unsigned long *fpr, unsigned long val) in validate_fpr() argument
48 if (fpr[i] != val) { in validate_fpr()
49 printf("FPR[%d]: %lx Expected: %lx\n", i, fpr[i], val); in validate_fpr()
60 int validate_fpr_float(float *fpr, float val) in validate_fpr_float() argument
65 if (fpr[i] != val) { in validate_fpr_float()
66 printf("FPR[%d]: %f Expected: %f\n", i, fpr[i], val); in validate_fpr_float()
Dptrace-tm-gpr.c94 unsigned long fpr[32]; in trace_tm_gpr() local
99 FAIL_IF(show_fpr(child, fpr)); in trace_tm_gpr()
100 FAIL_IF(validate_fpr(fpr, FPR_2_REP)); in trace_tm_gpr()
101 FAIL_IF(show_ckpt_fpr(child, fpr)); in trace_tm_gpr()
102 FAIL_IF(validate_fpr(fpr, FPR_1_REP)); in trace_tm_gpr()
Dptrace-tm-spd-gpr.c100 unsigned long fpr[32]; in trace_tm_spd_gpr() local
105 FAIL_IF(show_fpr(child, fpr)); in trace_tm_spd_gpr()
106 FAIL_IF(validate_fpr(fpr, FPR_4_REP)); in trace_tm_spd_gpr()
107 FAIL_IF(show_ckpt_fpr(child, fpr)); in trace_tm_spd_gpr()
108 FAIL_IF(validate_fpr(fpr, FPR_1_REP)); in trace_tm_spd_gpr()
Dptrace.h37 unsigned long fpr[32]; member
325 int show_fpr(pid_t child, unsigned long *fpr) in show_fpr() argument
337 if (fpr) { in show_fpr()
339 fpr[i] = regs->fpr[i]; in show_fpr()
357 regs->fpr[i] = val; in write_fpr()
367 int show_ckpt_fpr(pid_t child, unsigned long *fpr) in show_ckpt_fpr() argument
383 if (fpr) { in show_ckpt_fpr()
385 fpr[i] = regs->fpr[i]; in show_ckpt_fpr()
408 regs->fpr[i] = val; in write_ckpt_fpr()
Dptrace-gpr.c62 unsigned long fpr[32]; in trace_gpr() local
67 FAIL_IF(show_fpr(child, fpr)); in trace_gpr()
68 FAIL_IF(validate_fpr(fpr, FPR_1_REP)); in trace_gpr()
/external/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-regbankselect.mir77 # Based on the type <2 x i32>, this should be fpr.
82 # CHECK-NEXT: - { id: 0, class: fpr }
99 # CHECK-NEXT: - { id: 0, class: fpr }
119 # CHECK-NEXT: - { id: 0, class: fpr }
146 # CHECK-NEXT: - { id: 1, class: fpr }
150 - { id: 1, class: fpr }
240 # G_OR instruction from fpr to gpr.
248 # FAST-NEXT: - { id: 2, class: fpr }
250 # FAST-NEXT: - { id: 3, class: fpr }
251 # FAST-NEXT: - { id: 4, class: fpr }
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AArch64/
Dregister-operand-bank.mir11 # CHECK: - { id: 1, class: fpr, preferred-register: '' }
18 %3 : fpr(s64) = COPY $d0
19 $d1 = COPY %3 : fpr
/external/libffi/src/mips/
Dffi.c767 double *fpr) in ffi_closure_mips_inner_O32() argument
801 avaluep[i] = ((char *) &fpr[i]) + sizeof (float); in ffi_closure_mips_inner_O32()
804 avaluep[i] = (char *) &fpr[i]; in ffi_closure_mips_inner_O32()
868 ffi_arg *fpr, int soft_float) in copy_struct_N32() argument
886 fpp = (char *)(argn >= 8 ? ar + argn : fpr + argn); in copy_struct_N32()
921 ffi_arg *fpr) in ffi_closure_mips_inner_N32() argument
959 argp = (argn >= 8 || soft_float) ? ar + argn : fpr + argn; in ffi_closure_mips_inner_N32()
1028 argn, 0, ar, fpr, soft_float); in ffi_closure_mips_inner_N32()
/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dffi.c767 double *fpr) in ffi_closure_mips_inner_O32() argument
801 avaluep[i] = ((char *) &fpr[i]) + sizeof (float); in ffi_closure_mips_inner_O32()
804 avaluep[i] = (char *) &fpr[i]; in ffi_closure_mips_inner_O32()
868 ffi_arg *fpr, int soft_float) in copy_struct_N32() argument
886 fpp = (char *)(argn >= 8 ? ar + argn : fpr + argn); in copy_struct_N32()
921 ffi_arg *fpr) in ffi_closure_mips_inner_N32() argument
959 argp = (argn >= 8 || soft_float) ? ar + argn : fpr + argn; in ffi_closure_mips_inner_N32()
1028 argn, 0, ar, fpr, soft_float); in ffi_closure_mips_inner_N32()
/external/elfutils/backends/
Ds390_initreg.c77 } fpr = { .d = user_regs.regs.fp_regs.fprs[u] }; in s390_set_initial_registers_tid()
78 dwarf_regs[u] = fpr.w; in s390_set_initial_registers_tid()

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