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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dfsqrt.ll1 ; fsqrt should be generated when the fsqrt feature is enabled, but not
4 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
5 ; RUN: grep {fsqrt f1, f1}
7 ; RUN: grep {fsqrt f1, f1}
8 ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
9 ; RUN: not grep {fsqrt f1, f1}
11 ; RUN: not grep {fsqrt f1, f1}
/external/llvm/test/CodeGen/PowerPC/
Dfsqrt.ll1 ; fsqrt should be generated when the fsqrt feature is enabled, but not
4 ; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
5 ; RUN: grep "fsqrt f1, f1"
7 ; RUN: grep "fsqrt f1, f1"
8 ; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
9 ; RUN: not grep "fsqrt f1, f1"
11 ; RUN: not grep "fsqrt f1, f1"
Dvec_sqrt.ll1 ; RUN: llc -mcpu=pwr6 -mattr=+altivec,+fsqrt < %s | FileCheck %s
4 ; does not provide an fsqrt instruction for vector.
59 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
60 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
68 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
69 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
70 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
71 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfsqrt.ll1 ; fsqrt should be generated when the fsqrt feature is enabled, but not
4 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
5 ; RUN: grep "fsqrt f1, f1"
7 ; RUN: grep "fsqrt f1, f1"
8 ; RUN: llc -verify-machineinstrs < %s -mattr=-vsx -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
9 ; RUN: not grep "fsqrt f1, f1"
11 ; RUN: not grep "fsqrt f1, f1"
Dvec_sqrt.ll1 ; RUN: llc -verify-machineinstrs -mcpu=pwr6 -mattr=+altivec,+fsqrt < %s | FileCheck %s
4 ; does not provide an fsqrt instruction for vector.
59 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
60 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
68 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
69 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
70 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
71 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
/external/llvm/test/CodeGen/AArch64/
Dsqrt-fastmath.ll12 define float @fsqrt(float %a) #0 {
16 ; FAULT-LABEL: fsqrt:
18 ; FAULT-NEXT: fsqrt
20 ; CHECK-LABEL: fsqrt:
32 ; FAULT-NEXT: fsqrt
47 ; FAULT-NEXT: fsqrt
62 ; FAULT-NEXT: fsqrt
76 ; FAULT-NEXT: fsqrt
92 ; FAULT-NEXT: fsqrt
107 ; FAULT-NEXT: fsqrt
[all …]
Dfast-isel-sqrt.ll6 ; CHECK: fsqrt s0, s0
14 ; CHECK: fsqrt d0, d0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dfsqrt.s10 fsqrt z31.h, p7/m, z31.h label
16 fsqrt z31.s, p7/m, z31.s label
22 fsqrt z31.d, p7/m, z31.d label
38 fsqrt z4.d, p7/m, z31.d label
50 fsqrt z4.d, p7/m, z31.d label
Dfsqrt-diagnostics.s3 fsqrt z0.b, p0/m, z0.b label
8 fsqrt z0.s, p0/z, z0.s label
13 fsqrt z0.s, p8/m, z0.s label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dsqrt-fastmath.ll13 define float @fsqrt(float %a) #0 {
14 ; FAULT-LABEL: fsqrt:
16 ; FAULT-NEXT: fsqrt s0, s0
19 ; CHECK-LABEL: fsqrt:
39 ; FAULT-NEXT: fsqrt s0, s0
62 ; FAULT-NEXT: fsqrt v0.2s, v0.2s
86 ; FAULT-NEXT: fsqrt v0.4s, v0.4s
110 ; FAULT-NEXT: fsqrt v0.4s, v0.4s
111 ; FAULT-NEXT: fsqrt v1.4s, v1.4s
146 ; FAULT-NEXT: fsqrt d0, d0
[all …]
Dfast-isel-sqrt.ll6 ; CHECK: fsqrt s0, s0
14 ; CHECK: fsqrt d0, d0
Dfp16_intrinsic_vector_1op.ll28 ; CHECK: fsqrt v0.4h, v0.4h
37 ; CHECK: fsqrt v0.8h, v0.8h
Darm64-vfloatintrinsics.ll12 ; CHECK: fsqrt.2s
18 ; CHECK: fsqrt s{{.}}, s{{.}}
19 ; CHECK: fsqrt s{{.}}, s{{.}}
20 ; CHECK: fsqrt s{{.}}, s{{.}}
21 ; CHECK: fsqrt s{{.}}, s{{.}}
25 ; CHECK-FP16: fsqrt.4h
31 ; Filechecks are unwieldy with 16 fcvt and 8 fsqrt tests, so skipped for -fullfp16.
35 ; CHECK-FP16: fsqrt.8h
348 ; CHECK: fsqrt.4s
472 ; CHECK: fsqrt.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dsqrt-fastmath-tune.ll6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -O2 -mattr=+fast-scalar-fsqrt,-fast-vector-fsqrt | …
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -O2 -mattr=-fast-scalar-fsqrt,+fast-vector-fsqrt | …
/external/llvm/test/MC/Mips/msa/
Dtest_2rf.s25 # CHECK: fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
58 fsqrt.w $w0, $w11
59 fsqrt.d $w15, $w12
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_2rf.s25 # CHECK: fsqrt.w $w0, $w11 # encoding: [0x7b,0x26,0x58,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
58 fsqrt.w $w0, $w11
59 fsqrt.d $w15, $w12
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding-fp.s.cs47 0xfc,0x40,0x18,0x2c = fsqrt 2, 3
48 0xfc,0x40,0x18,0x2d = fsqrt. 2, 3
/external/capstone/suite/MC/Mips/
Dtest_2rf.s.cs24 0x7b,0x26,0x58,0x1e = fsqrt.w $w0, $w11
25 0x7b,0x27,0x63,0xde = fsqrt.d $w15, $w12
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
D2rf.ll252 %1 = tail call <4 x float> @llvm.mips.fsqrt.w(<4 x float> %0)
257 declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>) nounwind
262 ; CHECK-DAG: fsqrt.w [[WD:\$w[0-9]+]], [[WS]]
273 %1 = tail call <2 x double> @llvm.mips.fsqrt.d(<2 x double> %0)
278 declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>) nounwind
283 ; CHECK-DAG: fsqrt.d [[WD:\$w[0-9]+]], [[WS]]
301 ; CHECK-DAG: fsqrt.w [[WD:\$w[0-9]+]], [[WS]]
319 ; CHECK-DAG: fsqrt.d [[WD:\$w[0-9]+]], [[WS]]
/external/llvm/test/CodeGen/Mips/msa/
D2rf.ll252 %1 = tail call <4 x float> @llvm.mips.fsqrt.w(<4 x float> %0)
257 declare <4 x float> @llvm.mips.fsqrt.w(<4 x float>) nounwind
262 ; CHECK-DAG: fsqrt.w [[WD:\$w[0-9]+]], [[WS]]
273 %1 = tail call <2 x double> @llvm.mips.fsqrt.d(<2 x double> %0)
278 declare <2 x double> @llvm.mips.fsqrt.d(<2 x double>) nounwind
283 ; CHECK-DAG: fsqrt.d [[WD:\$w[0-9]+]], [[WS]]
301 ; CHECK-DAG: fsqrt.w [[WD:\$w[0-9]+]], [[WS]]
319 ; CHECK-DAG: fsqrt.d [[WD:\$w[0-9]+]], [[WS]]
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s154 # CHECK-BE: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c]
155 # CHECK-LE: fsqrt 2, 3 # encoding: [0x2c,0x18,0x40,0xfc]
156 fsqrt 2, 3
157 # CHECK-BE: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d]
158 # CHECK-LE: fsqrt. 2, 3 # encoding: [0x2d,0x18,0x40,0xfc]
159 fsqrt. 2, 3
/external/swiftshader/third_party/LLVM/test/MC/MBlaze/
Dmblaze_fpu.s29 # CHECK: fsqrt
32 fsqrt r0, r1
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding-fp.s154 # CHECK-BE: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c]
155 # CHECK-LE: fsqrt 2, 3 # encoding: [0x2c,0x18,0x40,0xfc]
156 fsqrt 2, 3
157 # CHECK-BE: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d]
158 # CHECK-LE: fsqrt. 2, 3 # encoding: [0x2d,0x18,0x40,0xfc]
159 fsqrt. 2, 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Drv32d-valid.s74 # CHECK-INST: fsqrt.d ft6, ft7, dyn
76 fsqrt.d ft6, ft7, dyn
150 # CHECK-INST: fsqrt.d ft6, ft7, rdn
152 fsqrt.d ft6, ft7, rdn
Drvd-aliases-valid.s74 # CHECK-INST: fsqrt.d ft6, ft7, dyn
75 # CHECK-ALIAS: fsqrt.d ft6, ft7{{[[:space:]]}}
76 fsqrt.d ft6, ft7

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