| /external/llvm/test/MC/Mips/msa/ |
| D | test_3rf.s | 67 # CHECK: fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda]
68 # CHECK: fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a]
150 fsun.w $w3, $w18, $w28
151 fsun.d $w18, $w11, $w19
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/ |
| D | test_3rf.s | 67 # CHECK: fsun.w $w3, $w18, $w28 # encoding: [0x7a,0x5c,0x90,0xda]
68 # CHECK: fsun.d $w18, $w11, $w19 # encoding: [0x7a,0x73,0x5c,0x9a]
150 fsun.w $w3, $w18, $w28
151 fsun.d $w18, $w11, $w19
|
| /external/ltp/testcases/kernel/syscalls/recvmsg/ |
| D | recvmsg01.c | 427 struct sockaddr_un fsun; in do_child() local
466 fromlen = sizeof(fsun); in do_child()
467 newfd = accept(ufd, (struct sockaddr *)&fsun, &fromlen); in do_child()
|
| /external/capstone/suite/MC/Mips/ |
| D | test_3rf.s.cs | 66 0x7a,0x5c,0x90,0xda = fsun.w $w3, $w18, $w28
67 0x7a,0x73,0x5c,0x9a = fsun.d $w18, $w11, $w19
|
| /external/ltp/testcases/kernel/syscalls/sendmsg/ |
| D | sendmsg01.c | 484 struct sockaddr_un fsun; in do_child() local
516 fromlen = sizeof(fsun); in do_child()
517 newfd = accept(ufd, (struct sockaddr *)&fsun, &fromlen); in do_child()
|
| /external/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_3rf.txt | 67 0x7a 0x5c 0x90 0xda # CHECK: fsun.w $w3, $w18, $w28
68 0x7a 0x73 0x5c 0x9a # CHECK: fsun.d $w18, $w11, $w19
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/msa/ |
| D | test_3rf.txt | 67 0x7a 0x5c 0x90 0xda # CHECK: fsun.w $w3, $w18, $w28
68 0x7a 0x73 0x5c 0x9a # CHECK: fsun.d $w18, $w11, $w19
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/ |
| D | 3rf_int_float.ll | 895 %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)
900 declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind
905 ; CHECK: fsun.w
917 %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)
922 declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind
927 ; CHECK: fsun.d
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| D | 3rf_int_float.ll | 895 %2 = tail call <4 x i32> @llvm.mips.fsun.w(<4 x float> %0, <4 x float> %1)
900 declare <4 x i32> @llvm.mips.fsun.w(<4 x float>, <4 x float>) nounwind
905 ; CHECK: fsun.w
917 %2 = tail call <2 x i64> @llvm.mips.fsun.d(<2 x double> %0, <2 x double> %1)
922 declare <2 x i64> @llvm.mips.fsun.d(<2 x double>, <2 x double>) nounwind
927 ; CHECK: fsun.d
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 2162 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2164 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsMSAInstrInfo.td | 2162 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2164 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
|
| /external/v8/src/mips/ |
| D | assembler-mips.cc | 3544 V(fsun, FSUN) \
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 4925 "fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d\007fsune.w\tftint_s.d"
6298 …{ 4820 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
6299 …{ 4827 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Fea…
9523 { Feature_HasStdEnc|Feature_HasMSA, 4820 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
9524 { Feature_HasStdEnc|Feature_HasMSA, 4827 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.cc | 3862 V(fsun, FSUN) \
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/ |
| D | IntrinsicEnums.inc | 3281 mips_fsun_d, // llvm.mips.fsun.d
3282 mips_fsun_w, // llvm.mips.fsun.w
|
| D | IntrinsicImpl.inc | 3307 "llvm.mips.fsun.d",
3308 "llvm.mips.fsun.w",
12185 1, // llvm.mips.fsun.d
12186 1, // llvm.mips.fsun.w
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 2522 mips_fsun_d, // llvm.mips.fsun.d
2523 mips_fsun_w, // llvm.mips.fsun.w
8580 "llvm.mips.fsun.d",
8581 "llvm.mips.fsun.w",
16520 1, // llvm.mips.fsun.d
16521 1, // llvm.mips.fsun.w
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 2522 mips_fsun_d, // llvm.mips.fsun.d
2523 mips_fsun_w, // llvm.mips.fsun.w
8580 "llvm.mips.fsun.d",
8581 "llvm.mips.fsun.w",
16520 1, // llvm.mips.fsun.d
16521 1, // llvm.mips.fsun.w
|
| /external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/ |
| D | Intrinsics.gen | 2522 mips_fsun_d, // llvm.mips.fsun.d
2523 mips_fsun_w, // llvm.mips.fsun.w
8580 "llvm.mips.fsun.d",
8581 "llvm.mips.fsun.w",
16520 1, // llvm.mips.fsun.d
16521 1, // llvm.mips.fsun.w
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 2516 mips_fsun_d, // llvm.mips.fsun.d
2517 mips_fsun_w, // llvm.mips.fsun.w
8540 "llvm.mips.fsun.d",
8541 "llvm.mips.fsun.w",
16425 1, // llvm.mips.fsun.d
16426 1, // llvm.mips.fsun.w
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 2522 mips_fsun_d, // llvm.mips.fsun.d
2523 mips_fsun_w, // llvm.mips.fsun.w
8580 "llvm.mips.fsun.d",
8581 "llvm.mips.fsun.w",
16520 1, // llvm.mips.fsun.d
16521 1, // llvm.mips.fsun.w
|