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/external/u-boot/arch/arm/dts/
Dsocfpga.dtsi292 compatible = "altr,socfpga-gate-clk";
294 clk-gate = <0x60 0>;
306 compatible = "altr,socfpga-gate-clk";
309 clk-gate = <0x60 1>;
314 compatible = "altr,socfpga-gate-clk";
321 compatible = "altr,socfpga-gate-clk";
324 clk-gate = <0x60 2>;
329 compatible = "altr,socfpga-gate-clk";
332 clk-gate = <0x60 3>;
337 compatible = "altr,socfpga-gate-clk";
[all …]
Dam35xx-clocks.dtsi13 compatible = "ti,am35xx-gate-clock";
21 compatible = "ti,gate-clock";
29 compatible = "ti,am35xx-gate-clock";
37 compatible = "ti,gate-clock";
45 compatible = "ti,am35xx-gate-clock";
53 compatible = "ti,gate-clock";
61 compatible = "ti,am35xx-gate-clock";
98 compatible = "ti,wait-gate-clock";
Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
511 compatible = "ti,composite-no-wait-gate-clock";
595 compatible = "ti,composite-gate-clock";
617 compatible = "ti,composite-gate-clock";
[all …]
Dam33xx-clocks.dtsi101 compatible = "ti,gate-clock";
109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
297 compatible = "ti,gate-clock";
321 compatible = "ti,gate-clock";
344 compatible = "ti,gate-clock";
401 compatible = "ti,gate-clock";
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
351 compatible = "ti,gate-clock";
504 compatible = "ti,gate-clock";
512 compatible = "ti,gate-clock";
520 compatible = "ti,gate-clock";
[all …]
Dsocfpga_arria10.dtsi335 compatible = "altr,socfpga-a10-gate-clk";
338 clk-gate = <0x48 1>;
343 compatible = "altr,socfpga-a10-gate-clk";
346 clk-gate = <0x48 2>;
351 compatible = "altr,socfpga-a10-gate-clk";
354 clk-gate = <0x48 3>;
359 compatible = "altr,socfpga-a10-gate-clk";
362 clk-gate = <0x48 0>;
367 compatible = "altr,socfpga-a10-gate-clk";
369 clk-gate = <0xC8 5>;
[all …]
Ddra7xx-clocks.dtsi1194 compatible = "ti,gate-clock";
1259 compatible = "ti,gate-clock";
1267 compatible = "ti,gate-clock";
1285 compatible = "ti,gate-clock";
1293 compatible = "ti,gate-clock";
1301 compatible = "ti,gate-clock";
1309 compatible = "ti,gate-clock";
1530 compatible = "ti,gate-clock";
1538 compatible = "ti,gate-clock";
1546 compatible = "ti,gate-clock";
[all …]
Domap34xx-omap36xx-clocks.dtsi53 compatible = "ti,gate-clock";
70 compatible = "ti,gate-clock";
134 compatible = "ti,wait-gate-clock";
142 compatible = "ti,wait-gate-clock";
187 compatible = "ti,wait-gate-clock";
219 compatible = "ti,wait-gate-clock";
/external/u-boot/arch/arm/cpu/armv7/bcm281xx/
Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
Dclk-bcm281xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/external/u-boot/arch/arm/cpu/armv7/bcm235xx/
Dclk-core.h95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
390 struct bcm_clk_gate gate; member
394 struct bcm_clk_gate gate; member
398 struct bcm_clk_gate gate; member
Dclk-bcm235xx.c131 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
144 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
156 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
168 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
180 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
193 .gate = SW_ONLY_GATE(0x0358, 20, 4),
198 .gate = SW_ONLY_GATE(0x035c, 20, 4),
203 .gate = SW_ONLY_GATE(0x0364, 20, 4),
[all …]
Dclk-core.c83 struct bcm_clk_gate *gate = &cd->gate; in peri_clk_enable() local
105 if (gate_exists(gate)) { in peri_clk_enable()
106 reg = readl(base + cd->gate.offset); in peri_clk_enable()
107 reg |= (1 << cd->gate.en_bit); in peri_clk_enable()
108 writel(reg, base + cd->gate.offset); in peri_clk_enable()
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); in peri_clk_enable()
145 reg = readl(base + cd->gate.offset); in peri_clk_enable()
146 reg &= ~(1 << cd->gate.en_bit); in peri_clk_enable()
147 writel(reg, base + cd->gate.offset); in peri_clk_enable()
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); in peri_clk_enable()
[all …]
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
/external/syzkaller/executor/
Dcommon_kvm_amd64.h183 struct kvm_segment gate; in setup_32bit_idt() local
184 gate.selector = i << 3; in setup_32bit_idt()
188 gate.type = 6; in setup_32bit_idt()
189 gate.base = SEL_CS16; in setup_32bit_idt()
193 gate.type = 7; in setup_32bit_idt()
194 gate.base = SEL_CS16; in setup_32bit_idt()
198 gate.type = 3; in setup_32bit_idt()
199 gate.base = SEL_TGATE16; in setup_32bit_idt()
203 gate.type = 14; in setup_32bit_idt()
204 gate.base = SEL_CS32; in setup_32bit_idt()
[all …]
/external/u-boot/arch/arm/mach-imx/mx7ulp/
Dscg.c169 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
173 gate = SCG_PLL_PFD0_GATE_MASK; in scg_apll_pfd_get_rate()
179 gate = SCG_PLL_PFD1_GATE_MASK; in scg_apll_pfd_get_rate()
185 gate = SCG_PLL_PFD2_GATE_MASK; in scg_apll_pfd_get_rate()
191 gate = SCG_PLL_PFD3_GATE_MASK; in scg_apll_pfd_get_rate()
201 if (reg & gate || !(reg & valid)) in scg_apll_pfd_get_rate()
219 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
223 gate = SCG_PLL_PFD0_GATE_MASK; in scg_spll_pfd_get_rate()
229 gate = SCG_PLL_PFD1_GATE_MASK; in scg_spll_pfd_get_rate()
235 gate = SCG_PLL_PFD2_GATE_MASK; in scg_spll_pfd_get_rate()
[all …]
/external/u-boot/drivers/clk/
Dclk_stm32mp1.c395 const struct stm32mp1_clk_gate *gate; member
707 .gate = stm32mp1_clk_gate,
728 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_id() local
732 if (gate[i].index == id) in stm32mp1_clk_get_id()
747 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_sel() local
749 if (gate[i].sel > _PARENT_SEL_NB) { in stm32mp1_clk_get_sel()
755 return gate[i].sel; in stm32mp1_clk_get_sel()
761 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_fixed_parent() local
763 if (gate[i].fixed == _UNKNOWN_ID) in stm32mp1_clk_get_fixed_parent()
766 return gate[i].fixed; in stm32mp1_clk_get_fixed_parent()
[all …]
Dclk_meson.c134 struct meson_gate *gate; in meson_set_gate() local
139 gate = &gates[clk->id]; in meson_set_gate()
141 if (gate->reg == 0) in meson_set_gate()
144 clrsetbits_le32(priv->addr + gate->reg, in meson_set_gate()
145 BIT(gate->bit), on ? BIT(gate->bit) : 0); in meson_set_gate()
/external/u-boot/arch/arm/mach-imx/
Drdc-sema.c66 &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
67 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_lock()
94 reg = readb(&imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
98 writeb(0x0, &imx_rdc_sema->gate[per_id % SEMA_GATES_NUM]); in imx_rdc_sema_unlock()
/external/u-boot/drivers/clk/uniphier/
Dclk-uniphier-core.c29 const struct uniphier_clk_gate_data *gate) in uniphier_clk_gate_enable() argument
33 val = readl(priv->base + gate->reg); in uniphier_clk_gate_enable()
34 val |= BIT(gate->bit); in uniphier_clk_gate_enable()
35 writel(val, priv->base + gate->reg); in uniphier_clk_gate_enable()
99 parent_id = data->data.gate.parent_id; in uniphier_clk_get_parent_data()
124 uniphier_clk_gate_enable(priv, &data->data.gate); in __uniphier_clk_enable()
/external/webrtc/webrtc/modules/audio_processing/agc/legacy/
Ddigital_agc.c312 int16_t gate, gain_adj; in WebRtcAgc_ProcessDigital() local
483 gate = 1000 + zeros_fast - zeros - stt->vadNearend.stdShortTerm; in WebRtcAgc_ProcessDigital()
485 if (gate < 0) in WebRtcAgc_ProcessDigital()
491 gate = (int16_t)((gate + tmp32) >> 3); in WebRtcAgc_ProcessDigital()
492 stt->gatePrevious = gate; in WebRtcAgc_ProcessDigital()
496 if (gate > 0) in WebRtcAgc_ProcessDigital()
498 if (gate < 2500) in WebRtcAgc_ProcessDigital()
500 gain_adj = (2500 - gate) >> 5; in WebRtcAgc_ProcessDigital()
/external/syzkaller/tools/syz-stress/
Dstress.go35 gate *ipc.Gate var
74 gate = ipc.NewGate(2**flagProcs, nil)
111 ticket := gate.Enter()
112 defer gate.Leave(ticket)

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