Searched refs:gb_tile_mode (Results 1 – 5 of 5) sorted by relevance
1072 static void si_gb_tile_mode(uint32_t gb_tile_mode, in si_gb_tile_mode() argument1081 switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) { in si_gb_tile_mode()1104 switch (SI__GB_TILE_MODE__NUM_BANKS(gb_tile_mode)) { in si_gb_tile_mode()1121 switch (SI__GB_TILE_MODE__MACRO_TILE_ASPECT(gb_tile_mode)) { in si_gb_tile_mode()1138 switch (SI__GB_TILE_MODE__BANK_WIDTH(gb_tile_mode)) { in si_gb_tile_mode()1155 switch (SI__GB_TILE_MODE__BANK_HEIGHT(gb_tile_mode)) { in si_gb_tile_mode()1172 switch (SI__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) { in si_gb_tile_mode()1290 uint32_t gb_tile_mode; in si_surface_sanity() local1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()1348 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split); in si_surface_sanity()[all …]
59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D]; in cik_get_num_tile_pipes()322 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, in ac_query_gpu_info()323 sizeof(amdinfo->gb_tile_mode)); in ac_query_gpu_info()
187 regValue.pTileConfig = amdinfo->gb_tile_mode; in amdgpu_addr_create()188 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); in amdgpu_addr_create()
463 uint32_t gb_tile_mode[32]; member
203 dev->info.gb_tile_mode); in amdgpu_query_gpu_info_init()