1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the pass that transforms the ARM machine instructions into
11 // relocatable machine code.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "jit"
16 #include "ARM.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMInstrInfo.h"
19 #include "ARMRelocations.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/JITCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #ifndef NDEBUG
39 #include <iomanip>
40 #endif
41 using namespace llvm;
42
43 STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45 namespace {
46
47 class ARMCodeEmitter : public MachineFunctionPass {
48 ARMJITInfo *JTI;
49 const ARMInstrInfo *II;
50 const TargetData *TD;
51 const ARMSubtarget *Subtarget;
52 TargetMachine &TM;
53 JITCodeEmitter &MCE;
54 MachineModuleInfo *MMI;
55 const std::vector<MachineConstantPoolEntry> *MCPEs;
56 const std::vector<MachineJumpTableEntry> *MJTEs;
57 bool IsPIC;
58 bool IsThumb;
59
getAnalysisUsage(AnalysisUsage & AU) const60 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
63 }
64
65 static char ID;
66 public:
ARMCodeEmitter(TargetMachine & tm,JITCodeEmitter & mce)67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68 : MachineFunctionPass(ID), JTI(0),
69 II((const ARMInstrInfo *)tm.getInstrInfo()),
70 TD(tm.getTargetData()), TM(tm),
71 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79 bool runOnMachineFunction(MachineFunction &MF);
80
getPassName() const81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
83 }
84
85 void emitInstruction(const MachineInstr &MI);
86
87 private:
88
89 void emitWordLE(unsigned Binary);
90 void emitDWordLE(uint64_t Binary);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
96 void addPCLabel(unsigned LabelID);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99 const MCInstrDesc &MCID,
100 const MachineOperand &MO,
101 unsigned OpIdx);
102
103 unsigned getMachineSoImmOpValue(unsigned SoImm);
104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const MCInstrDesc &MCID) const;
106
107 void emitDataProcessingInstruction(const MachineInstr &MI,
108 unsigned ImplicitRd = 0,
109 unsigned ImplicitRn = 0);
110
111 void emitLoadStoreInstruction(const MachineInstr &MI,
112 unsigned ImplicitRd = 0,
113 unsigned ImplicitRn = 0);
114
115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
117
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120 void emitMulFrmInstruction(const MachineInstr &MI);
121
122 void emitExtendInstruction(const MachineInstr &MI);
123
124 void emitMiscArithInstruction(const MachineInstr &MI);
125
126 void emitSaturateInstruction(const MachineInstr &MI);
127
128 void emitBranchInstruction(const MachineInstr &MI);
129
130 void emitInlineJumpTable(unsigned JTIndex);
131
132 void emitMiscBranchInstruction(const MachineInstr &MI);
133
134 void emitVFPArithInstruction(const MachineInstr &MI);
135
136 void emitVFPConversionInstruction(const MachineInstr &MI);
137
138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
142 void emitNEONLaneInstruction(const MachineInstr &MI);
143 void emitNEONDupInstruction(const MachineInstr &MI);
144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
146 void emitNEON3RegInstruction(const MachineInstr &MI);
147
148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
getMachineOpValue(const MachineInstr & MI,unsigned OpIdx) const152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
154 }
155
156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
NEONThumb2DataIPostEncoder(const MachineInstr & MI,unsigned Val) const164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165 const { return 0; }
NEONThumb2LoadStorePostEncoder(const MachineInstr & MI,unsigned Val) const166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167 const { return 0; }
NEONThumb2DupPostEncoder(const MachineInstr & MI,unsigned Val) const168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
169 const { return 0; }
VFPThumb2PostEncoder(const MachineInstr & MI,unsigned Val) const170 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
171 const { return 0; }
getAdrLabelOpValue(const MachineInstr & MI,unsigned Op) const172 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
173 const { return 0; }
getThumbAdrLabelOpValue(const MachineInstr & MI,unsigned Op) const174 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
175 const { return 0; }
getThumbBLTargetOpValue(const MachineInstr & MI,unsigned Op) const176 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
177 const { return 0; }
getThumbBLXTargetOpValue(const MachineInstr & MI,unsigned Op) const178 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
179 const { return 0; }
getThumbBRTargetOpValue(const MachineInstr & MI,unsigned Op) const180 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
181 const { return 0; }
getThumbBCCTargetOpValue(const MachineInstr & MI,unsigned Op) const182 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
183 const { return 0; }
getThumbCBTargetOpValue(const MachineInstr & MI,unsigned Op) const184 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
185 const { return 0; }
getBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const186 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
187 const { return 0; }
getUnconditionalBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const188 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189 unsigned Op) const { return 0; }
getARMBranchTargetOpValue(const MachineInstr & MI,unsigned Op) const190 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
191 const { return 0; }
getARMBLXTargetOpValue(const MachineInstr & MI,unsigned Op) const192 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
193 const { return 0; }
getCCOutOpValue(const MachineInstr & MI,unsigned Op) const194 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
195 const { return 0; }
getSOImmOpValue(const MachineInstr & MI,unsigned Op) const196 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
197 const { return 0; }
getT2SOImmOpValue(const MachineInstr & MI,unsigned Op) const198 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
199 const { return 0; }
getSORegRegOpValue(const MachineInstr & MI,unsigned Op) const200 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
201 const { return 0; }
getSORegImmOpValue(const MachineInstr & MI,unsigned Op) const202 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
203 const { return 0; }
getThumbAddrModeRegRegOpValue(const MachineInstr & MI,unsigned Op) const204 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
205 const { return 0; }
getT2AddrModeImm12OpValue(const MachineInstr & MI,unsigned Op) const206 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
207 const { return 0; }
getT2AddrModeImm8OpValue(const MachineInstr & MI,unsigned Op) const208 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
209 const { return 0; }
getT2Imm8s4OpValue(const MachineInstr & MI,unsigned Op) const210 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
211 const { return 0; }
getT2AddrModeImm8s4OpValue(const MachineInstr & MI,unsigned Op) const212 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
213 const { return 0; }
getT2AddrModeImm0_1020s4OpValue(const MachineInstr & MI,unsigned Op) const214 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
215 const { return 0; }
getT2AddrModeImm8OffsetOpValue(const MachineInstr & MI,unsigned Op) const216 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
217 const { return 0; }
getT2AddrModeImm12OffsetOpValue(const MachineInstr & MI,unsigned Op) const218 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
219 const { return 0; }
getT2AddrModeSORegOpValue(const MachineInstr & MI,unsigned Op) const220 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
221 const { return 0; }
getT2SORegOpValue(const MachineInstr & MI,unsigned Op) const222 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
223 const { return 0; }
getT2AdrLabelOpValue(const MachineInstr & MI,unsigned Op) const224 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
225 const { return 0; }
getAddrMode6AddressOpValue(const MachineInstr & MI,unsigned Op) const226 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
227 const { return 0; }
getAddrMode6OneLane32AddressOpValue(const MachineInstr & MI,unsigned Op) const228 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
229 unsigned Op)
230 const { return 0; }
getAddrMode6DupAddressOpValue(const MachineInstr & MI,unsigned Op) const231 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
232 const { return 0; }
getAddrMode6OffsetOpValue(const MachineInstr & MI,unsigned Op) const233 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
234 const { return 0; }
getBitfieldInvertedMaskOpValue(const MachineInstr & MI,unsigned Op) const235 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
236 unsigned Op) const { return 0; }
getSsatBitPosValue(const MachineInstr & MI,unsigned Op) const237 unsigned getSsatBitPosValue(const MachineInstr &MI,
238 unsigned Op) const { return 0; }
getLdStmModeOpValue(const MachineInstr & MI,unsigned OpIdx) const239 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
240 const {return 0; }
getLdStSORegOpValue(const MachineInstr & MI,unsigned OpIdx) const241 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
242 const { return 0; }
243
getAddrModeImm12OpValue(const MachineInstr & MI,unsigned Op) const244 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
245 const {
246 // {17-13} = reg
247 // {12} = (U)nsigned (add == '1', sub == '0')
248 // {11-0} = imm12
249 const MachineOperand &MO = MI.getOperand(Op);
250 const MachineOperand &MO1 = MI.getOperand(Op + 1);
251 if (!MO.isReg()) {
252 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
253 return 0;
254 }
255 unsigned Reg = getARMRegisterNumbering(MO.getReg());
256 int32_t Imm12 = MO1.getImm();
257 uint32_t Binary;
258 Binary = Imm12 & 0xfff;
259 if (Imm12 >= 0)
260 Binary |= (1 << 12);
261 Binary |= (Reg << 13);
262 return Binary;
263 }
264
getHiLo16ImmOpValue(const MachineInstr & MI,unsigned Op) const265 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
266 return 0;
267 }
268
getAddrMode2OpValue(const MachineInstr & MI,unsigned OpIdx) const269 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
270 const { return 0;}
getAddrMode2OffsetOpValue(const MachineInstr & MI,unsigned OpIdx) const271 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
272 const { return 0;}
getPostIdxRegOpValue(const MachineInstr & MI,unsigned OpIdx) const273 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
274 const { return 0;}
getAddrMode3OffsetOpValue(const MachineInstr & MI,unsigned OpIdx) const275 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
276 const { return 0;}
getAddrMode3OpValue(const MachineInstr & MI,unsigned Op) const277 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
278 const { return 0; }
getAddrModeThumbSPOpValue(const MachineInstr & MI,unsigned Op) const279 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
280 const { return 0; }
getAddrModeSOpValue(const MachineInstr & MI,unsigned Op) const281 uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
282 const { return 0; }
getAddrModeISOpValue(const MachineInstr & MI,unsigned Op) const283 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
284 const { return 0; }
getAddrModePCOpValue(const MachineInstr & MI,unsigned Op) const285 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
286 const { return 0; }
getAddrMode5OpValue(const MachineInstr & MI,unsigned Op) const287 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
288 // {17-13} = reg
289 // {12} = (U)nsigned (add == '1', sub == '0')
290 // {11-0} = imm12
291 const MachineOperand &MO = MI.getOperand(Op);
292 const MachineOperand &MO1 = MI.getOperand(Op + 1);
293 if (!MO.isReg()) {
294 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
295 return 0;
296 }
297 unsigned Reg = getARMRegisterNumbering(MO.getReg());
298 int32_t Imm12 = MO1.getImm();
299
300 // Special value for #-0
301 if (Imm12 == INT32_MIN)
302 Imm12 = 0;
303
304 // Immediate is always encoded as positive. The 'U' bit controls add vs
305 // sub.
306 bool isAdd = true;
307 if (Imm12 < 0) {
308 Imm12 = -Imm12;
309 isAdd = false;
310 }
311
312 uint32_t Binary = Imm12 & 0xfff;
313 if (isAdd)
314 Binary |= (1 << 12);
315 Binary |= (Reg << 13);
316 return Binary;
317 }
getNEONVcvtImm32OpValue(const MachineInstr & MI,unsigned Op) const318 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
319 const { return 0; }
320
getRegisterListOpValue(const MachineInstr & MI,unsigned Op) const321 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
322 const { return 0; }
323
getShiftRight8Imm(const MachineInstr & MI,unsigned Op) const324 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
325 const { return 0; }
getShiftRight16Imm(const MachineInstr & MI,unsigned Op) const326 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
327 const { return 0; }
getShiftRight32Imm(const MachineInstr & MI,unsigned Op) const328 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
329 const { return 0; }
getShiftRight64Imm(const MachineInstr & MI,unsigned Op) const330 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
331 const { return 0; }
332
333 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
334 /// machine operand requires relocation, record the relocation and return
335 /// zero.
336 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
337 unsigned Reloc);
338
339 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
340 ///
341 unsigned getShiftOp(unsigned Imm) const ;
342
343 /// Routines that handle operands which add machine relocations which are
344 /// fixed up by the relocation stage.
345 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
346 bool MayNeedFarStub, bool Indirect,
347 intptr_t ACPV = 0) const;
348 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
349 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
350 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
351 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
352 intptr_t JTBase = 0) const;
353 };
354 }
355
356 char ARMCodeEmitter::ID = 0;
357
358 /// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
359 /// code to the specified MCE object.
createARMJITCodeEmitterPass(ARMBaseTargetMachine & TM,JITCodeEmitter & JCE)360 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
361 JITCodeEmitter &JCE) {
362 return new ARMCodeEmitter(TM, JCE);
363 }
364
runOnMachineFunction(MachineFunction & MF)365 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
366 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
367 MF.getTarget().getRelocationModel() != Reloc::Static) &&
368 "JIT relocation model must be set to static or default!");
369 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
370 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
371 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
372 Subtarget = &TM.getSubtarget<ARMSubtarget>();
373 MCPEs = &MF.getConstantPool()->getConstants();
374 MJTEs = 0;
375 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
376 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
377 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
378 JTI->Initialize(MF, IsPIC);
379 MMI = &getAnalysis<MachineModuleInfo>();
380 MCE.setModuleInfo(MMI);
381
382 do {
383 DEBUG(errs() << "JITTing function '"
384 << MF.getFunction()->getName() << "'\n");
385 MCE.startFunction(MF);
386 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
387 MBB != E; ++MBB) {
388 MCE.StartMachineBasicBlock(MBB);
389 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
390 I != E; ++I)
391 emitInstruction(*I);
392 }
393 } while (MCE.finishFunction(MF));
394
395 return false;
396 }
397
398 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
399 ///
getShiftOp(unsigned Imm) const400 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
401 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
402 default: llvm_unreachable("Unknown shift opc!");
403 case ARM_AM::asr: return 2;
404 case ARM_AM::lsl: return 0;
405 case ARM_AM::lsr: return 1;
406 case ARM_AM::ror:
407 case ARM_AM::rrx: return 3;
408 }
409 return 0;
410 }
411
412 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
413 /// machine operand requires relocation, record the relocation and return zero.
getMovi32Value(const MachineInstr & MI,const MachineOperand & MO,unsigned Reloc)414 unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
415 const MachineOperand &MO,
416 unsigned Reloc) {
417 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
418 && "Relocation to this function should be for movt or movw");
419
420 if (MO.isImm())
421 return static_cast<unsigned>(MO.getImm());
422 else if (MO.isGlobal())
423 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
424 else if (MO.isSymbol())
425 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
426 else if (MO.isMBB())
427 emitMachineBasicBlock(MO.getMBB(), Reloc);
428 else {
429 #ifndef NDEBUG
430 errs() << MO;
431 #endif
432 llvm_unreachable("Unsupported operand type for movw/movt");
433 }
434 return 0;
435 }
436
437 /// getMachineOpValue - Return binary encoding of operand. If the machine
438 /// operand requires relocation, record the relocation and return zero.
getMachineOpValue(const MachineInstr & MI,const MachineOperand & MO) const439 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
440 const MachineOperand &MO) const {
441 if (MO.isReg())
442 return getARMRegisterNumbering(MO.getReg());
443 else if (MO.isImm())
444 return static_cast<unsigned>(MO.getImm());
445 else if (MO.isGlobal())
446 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
447 else if (MO.isSymbol())
448 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
449 else if (MO.isCPI()) {
450 const MCInstrDesc &MCID = MI.getDesc();
451 // For VFP load, the immediate offset is multiplied by 4.
452 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
453 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
454 emitConstPoolAddress(MO.getIndex(), Reloc);
455 } else if (MO.isJTI())
456 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
457 else if (MO.isMBB())
458 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
459 else
460 llvm_unreachable("Unable to encode MachineOperand!");
461 return 0;
462 }
463
464 /// emitGlobalAddress - Emit the specified address to the code stream.
465 ///
emitGlobalAddress(const GlobalValue * GV,unsigned Reloc,bool MayNeedFarStub,bool Indirect,intptr_t ACPV) const466 void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
467 bool MayNeedFarStub, bool Indirect,
468 intptr_t ACPV) const {
469 MachineRelocation MR = Indirect
470 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
471 const_cast<GlobalValue *>(GV),
472 ACPV, MayNeedFarStub)
473 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
474 const_cast<GlobalValue *>(GV), ACPV,
475 MayNeedFarStub);
476 MCE.addRelocation(MR);
477 }
478
479 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
480 /// be emitted to the current location in the function, and allow it to be PC
481 /// relative.
482 void ARMCodeEmitter::
emitExternalSymbolAddress(const char * ES,unsigned Reloc) const483 emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
484 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
485 Reloc, ES));
486 }
487
488 /// emitConstPoolAddress - Arrange for the address of an constant pool
489 /// to be emitted to the current location in the function, and allow it to be PC
490 /// relative.
emitConstPoolAddress(unsigned CPI,unsigned Reloc) const491 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
492 // Tell JIT emitter we'll resolve the address.
493 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
494 Reloc, CPI, 0, true));
495 }
496
497 /// emitJumpTableAddress - Arrange for the address of a jump table to
498 /// be emitted to the current location in the function, and allow it to be PC
499 /// relative.
500 void ARMCodeEmitter::
emitJumpTableAddress(unsigned JTIndex,unsigned Reloc) const501 emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
502 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
503 Reloc, JTIndex, 0, true));
504 }
505
506 /// emitMachineBasicBlock - Emit the specified address basic block.
emitMachineBasicBlock(MachineBasicBlock * BB,unsigned Reloc,intptr_t JTBase) const507 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
508 unsigned Reloc,
509 intptr_t JTBase) const {
510 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
511 Reloc, BB, JTBase));
512 }
513
emitWordLE(unsigned Binary)514 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
515 DEBUG(errs() << " 0x";
516 errs().write_hex(Binary) << "\n");
517 MCE.emitWordLE(Binary);
518 }
519
emitDWordLE(uint64_t Binary)520 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
521 DEBUG(errs() << " 0x";
522 errs().write_hex(Binary) << "\n");
523 MCE.emitDWordLE(Binary);
524 }
525
emitInstruction(const MachineInstr & MI)526 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
527 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
528
529 MCE.processDebugLoc(MI.getDebugLoc(), true);
530
531 ++NumEmitted; // Keep track of the # of mi's emitted
532 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
533 default: {
534 llvm_unreachable("Unhandled instruction encoding format!");
535 break;
536 }
537 case ARMII::MiscFrm:
538 if (MI.getOpcode() == ARM::LEApcrelJT) {
539 // Materialize jumptable address.
540 emitLEApcrelJTInstruction(MI);
541 break;
542 }
543 llvm_unreachable("Unhandled instruction encoding!");
544 break;
545 case ARMII::Pseudo:
546 emitPseudoInstruction(MI);
547 break;
548 case ARMII::DPFrm:
549 case ARMII::DPSoRegFrm:
550 emitDataProcessingInstruction(MI);
551 break;
552 case ARMII::LdFrm:
553 case ARMII::StFrm:
554 emitLoadStoreInstruction(MI);
555 break;
556 case ARMII::LdMiscFrm:
557 case ARMII::StMiscFrm:
558 emitMiscLoadStoreInstruction(MI);
559 break;
560 case ARMII::LdStMulFrm:
561 emitLoadStoreMultipleInstruction(MI);
562 break;
563 case ARMII::MulFrm:
564 emitMulFrmInstruction(MI);
565 break;
566 case ARMII::ExtFrm:
567 emitExtendInstruction(MI);
568 break;
569 case ARMII::ArithMiscFrm:
570 emitMiscArithInstruction(MI);
571 break;
572 case ARMII::SatFrm:
573 emitSaturateInstruction(MI);
574 break;
575 case ARMII::BrFrm:
576 emitBranchInstruction(MI);
577 break;
578 case ARMII::BrMiscFrm:
579 emitMiscBranchInstruction(MI);
580 break;
581 // VFP instructions.
582 case ARMII::VFPUnaryFrm:
583 case ARMII::VFPBinaryFrm:
584 emitVFPArithInstruction(MI);
585 break;
586 case ARMII::VFPConv1Frm:
587 case ARMII::VFPConv2Frm:
588 case ARMII::VFPConv3Frm:
589 case ARMII::VFPConv4Frm:
590 case ARMII::VFPConv5Frm:
591 emitVFPConversionInstruction(MI);
592 break;
593 case ARMII::VFPLdStFrm:
594 emitVFPLoadStoreInstruction(MI);
595 break;
596 case ARMII::VFPLdStMulFrm:
597 emitVFPLoadStoreMultipleInstruction(MI);
598 break;
599
600 // NEON instructions.
601 case ARMII::NGetLnFrm:
602 case ARMII::NSetLnFrm:
603 emitNEONLaneInstruction(MI);
604 break;
605 case ARMII::NDupFrm:
606 emitNEONDupInstruction(MI);
607 break;
608 case ARMII::N1RegModImmFrm:
609 emitNEON1RegModImmInstruction(MI);
610 break;
611 case ARMII::N2RegFrm:
612 emitNEON2RegInstruction(MI);
613 break;
614 case ARMII::N3RegFrm:
615 emitNEON3RegInstruction(MI);
616 break;
617 }
618 MCE.processDebugLoc(MI.getDebugLoc(), false);
619 }
620
emitConstPoolInstruction(const MachineInstr & MI)621 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
622 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
623 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
624 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
625
626 // Remember the CONSTPOOL_ENTRY address for later relocation.
627 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
628
629 // Emit constpool island entry. In most cases, the actual values will be
630 // resolved and relocated after code emission.
631 if (MCPE.isMachineConstantPoolEntry()) {
632 ARMConstantPoolValue *ACPV =
633 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
634
635 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
636 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
637
638 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
639 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
640 if (GV) {
641 Reloc::Model RelocM = TM.getRelocationModel();
642 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
643 isa<Function>(GV),
644 Subtarget->GVIsIndirectSymbol(GV, RelocM),
645 (intptr_t)ACPV);
646 } else {
647 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
648 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
649 }
650 emitWordLE(0);
651 } else {
652 const Constant *CV = MCPE.Val.ConstVal;
653
654 DEBUG({
655 errs() << " ** Constant pool #" << CPI << " @ "
656 << (void*)MCE.getCurrentPCValue() << " ";
657 if (const Function *F = dyn_cast<Function>(CV))
658 errs() << F->getName();
659 else
660 errs() << *CV;
661 errs() << '\n';
662 });
663
664 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
665 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
666 emitWordLE(0);
667 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
668 uint32_t Val = uint32_t(*CI->getValue().getRawData());
669 emitWordLE(Val);
670 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
671 if (CFP->getType()->isFloatTy())
672 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
673 else if (CFP->getType()->isDoubleTy())
674 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
675 else {
676 llvm_unreachable("Unable to handle this constantpool entry!");
677 }
678 } else {
679 llvm_unreachable("Unable to handle this constantpool entry!");
680 }
681 }
682 }
683
emitMOVi32immInstruction(const MachineInstr & MI)684 void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
685 const MachineOperand &MO0 = MI.getOperand(0);
686 const MachineOperand &MO1 = MI.getOperand(1);
687
688 // Emit the 'movw' instruction.
689 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
690
691 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
692
693 // Set the conditional execution predicate.
694 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
695
696 // Encode Rd.
697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
698
699 // Encode imm16 as imm4:imm12
700 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
701 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
702 emitWordLE(Binary);
703
704 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
705 // Emit the 'movt' instruction.
706 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
707
708 // Set the conditional execution predicate.
709 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
710
711 // Encode Rd.
712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
713
714 // Encode imm16 as imm4:imm1, same as movw above.
715 Binary |= Hi16 & 0xFFF;
716 Binary |= ((Hi16 >> 12) & 0xF) << 16;
717 emitWordLE(Binary);
718 }
719
emitMOVi2piecesInstruction(const MachineInstr & MI)720 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
721 const MachineOperand &MO0 = MI.getOperand(0);
722 const MachineOperand &MO1 = MI.getOperand(1);
723 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
724 "Not a valid so_imm value!");
725 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
726 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
727
728 // Emit the 'mov' instruction.
729 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
730
731 // Set the conditional execution predicate.
732 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
733
734 // Encode Rd.
735 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
736
737 // Encode so_imm.
738 // Set bit I(25) to identify this is the immediate form of <shifter_op>
739 Binary |= 1 << ARMII::I_BitShift;
740 Binary |= getMachineSoImmOpValue(V1);
741 emitWordLE(Binary);
742
743 // Now the 'orr' instruction.
744 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
745
746 // Set the conditional execution predicate.
747 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
748
749 // Encode Rd.
750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
751
752 // Encode Rn.
753 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
754
755 // Encode so_imm.
756 // Set bit I(25) to identify this is the immediate form of <shifter_op>
757 Binary |= 1 << ARMII::I_BitShift;
758 Binary |= getMachineSoImmOpValue(V2);
759 emitWordLE(Binary);
760 }
761
emitLEApcrelJTInstruction(const MachineInstr & MI)762 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
763 // It's basically add r, pc, (LJTI - $+8)
764
765 const MCInstrDesc &MCID = MI.getDesc();
766
767 // Emit the 'add' instruction.
768 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
769
770 // Set the conditional execution predicate
771 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
772
773 // Encode S bit if MI modifies CPSR.
774 Binary |= getAddrModeSBit(MI, MCID);
775
776 // Encode Rd.
777 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
778
779 // Encode Rn which is PC.
780 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
781
782 // Encode the displacement.
783 Binary |= 1 << ARMII::I_BitShift;
784 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
785
786 emitWordLE(Binary);
787 }
788
emitPseudoMoveInstruction(const MachineInstr & MI)789 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
790 unsigned Opcode = MI.getDesc().Opcode;
791
792 // Part of binary is determined by TableGn.
793 unsigned Binary = getBinaryCodeForInstr(MI);
794
795 // Set the conditional execution predicate
796 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
797
798 // Encode S bit if MI modifies CPSR.
799 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
800 Binary |= 1 << ARMII::S_BitShift;
801
802 // Encode register def if there is one.
803 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
804
805 // Encode the shift operation.
806 switch (Opcode) {
807 default: break;
808 case ARM::RRX:
809 // rrx
810 Binary |= 0x6 << 4;
811 break;
812 case ARM::MOVsrl_flag:
813 // lsr #1
814 Binary |= (0x2 << 4) | (1 << 7);
815 break;
816 case ARM::MOVsra_flag:
817 // asr #1
818 Binary |= (0x4 << 4) | (1 << 7);
819 break;
820 }
821
822 // Encode register Rm.
823 Binary |= getMachineOpValue(MI, 1);
824
825 emitWordLE(Binary);
826 }
827
addPCLabel(unsigned LabelID)828 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
829 DEBUG(errs() << " ** LPC" << LabelID << " @ "
830 << (void*)MCE.getCurrentPCValue() << '\n');
831 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
832 }
833
emitPseudoInstruction(const MachineInstr & MI)834 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
835 unsigned Opcode = MI.getDesc().Opcode;
836 switch (Opcode) {
837 default:
838 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
839 case ARM::BX_CALL:
840 case ARM::BMOVPCRX_CALL:
841 case ARM::BXr9_CALL:
842 case ARM::BMOVPCRXr9_CALL: {
843 // First emit mov lr, pc
844 unsigned Binary = 0x01a0e00f;
845 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
846 emitWordLE(Binary);
847
848 // and then emit the branch.
849 emitMiscBranchInstruction(MI);
850 break;
851 }
852 case TargetOpcode::INLINEASM: {
853 // We allow inline assembler nodes with empty bodies - they can
854 // implicitly define registers, which is ok for JIT.
855 if (MI.getOperand(0).getSymbolName()[0]) {
856 report_fatal_error("JIT does not support inline asm!");
857 }
858 break;
859 }
860 case TargetOpcode::PROLOG_LABEL:
861 case TargetOpcode::EH_LABEL:
862 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
863 break;
864 case TargetOpcode::IMPLICIT_DEF:
865 case TargetOpcode::KILL:
866 // Do nothing.
867 break;
868 case ARM::CONSTPOOL_ENTRY:
869 emitConstPoolInstruction(MI);
870 break;
871 case ARM::PICADD: {
872 // Remember of the address of the PC label for relocation later.
873 addPCLabel(MI.getOperand(2).getImm());
874 // PICADD is just an add instruction that implicitly read pc.
875 emitDataProcessingInstruction(MI, 0, ARM::PC);
876 break;
877 }
878 case ARM::PICLDR:
879 case ARM::PICLDRB:
880 case ARM::PICSTR:
881 case ARM::PICSTRB: {
882 // Remember of the address of the PC label for relocation later.
883 addPCLabel(MI.getOperand(2).getImm());
884 // These are just load / store instructions that implicitly read pc.
885 emitLoadStoreInstruction(MI, 0, ARM::PC);
886 break;
887 }
888 case ARM::PICLDRH:
889 case ARM::PICLDRSH:
890 case ARM::PICLDRSB:
891 case ARM::PICSTRH: {
892 // Remember of the address of the PC label for relocation later.
893 addPCLabel(MI.getOperand(2).getImm());
894 // These are just load / store instructions that implicitly read pc.
895 emitMiscLoadStoreInstruction(MI, ARM::PC);
896 break;
897 }
898
899 case ARM::MOVi32imm:
900 // Two instructions to materialize a constant.
901 if (Subtarget->hasV6T2Ops())
902 emitMOVi32immInstruction(MI);
903 else
904 emitMOVi2piecesInstruction(MI);
905 break;
906
907 case ARM::LEApcrelJT:
908 // Materialize jumptable address.
909 emitLEApcrelJTInstruction(MI);
910 break;
911 case ARM::RRX:
912 case ARM::MOVsrl_flag:
913 case ARM::MOVsra_flag:
914 emitPseudoMoveInstruction(MI);
915 break;
916 }
917 }
918
getMachineSoRegOpValue(const MachineInstr & MI,const MCInstrDesc & MCID,const MachineOperand & MO,unsigned OpIdx)919 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
920 const MCInstrDesc &MCID,
921 const MachineOperand &MO,
922 unsigned OpIdx) {
923 unsigned Binary = getMachineOpValue(MI, MO);
924
925 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
926 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
927 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
928
929 // Encode the shift opcode.
930 unsigned SBits = 0;
931 unsigned Rs = MO1.getReg();
932 if (Rs) {
933 // Set shift operand (bit[7:4]).
934 // LSL - 0001
935 // LSR - 0011
936 // ASR - 0101
937 // ROR - 0111
938 // RRX - 0110 and bit[11:8] clear.
939 switch (SOpc) {
940 default: llvm_unreachable("Unknown shift opc!");
941 case ARM_AM::lsl: SBits = 0x1; break;
942 case ARM_AM::lsr: SBits = 0x3; break;
943 case ARM_AM::asr: SBits = 0x5; break;
944 case ARM_AM::ror: SBits = 0x7; break;
945 case ARM_AM::rrx: SBits = 0x6; break;
946 }
947 } else {
948 // Set shift operand (bit[6:4]).
949 // LSL - 000
950 // LSR - 010
951 // ASR - 100
952 // ROR - 110
953 switch (SOpc) {
954 default: llvm_unreachable("Unknown shift opc!");
955 case ARM_AM::lsl: SBits = 0x0; break;
956 case ARM_AM::lsr: SBits = 0x2; break;
957 case ARM_AM::asr: SBits = 0x4; break;
958 case ARM_AM::ror: SBits = 0x6; break;
959 }
960 }
961 Binary |= SBits << 4;
962 if (SOpc == ARM_AM::rrx)
963 return Binary;
964
965 // Encode the shift operation Rs or shift_imm (except rrx).
966 if (Rs) {
967 // Encode Rs bit[11:8].
968 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
969 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
970 }
971
972 // Encode shift_imm bit[11:7].
973 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
974 }
975
getMachineSoImmOpValue(unsigned SoImm)976 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
977 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
978 assert(SoImmVal != -1 && "Not a valid so_imm value!");
979
980 // Encode rotate_imm.
981 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
982 << ARMII::SoRotImmShift;
983
984 // Encode immed_8.
985 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
986 return Binary;
987 }
988
getAddrModeSBit(const MachineInstr & MI,const MCInstrDesc & MCID) const989 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
990 const MCInstrDesc &MCID) const {
991 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
992 const MachineOperand &MO = MI.getOperand(i-1);
993 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
994 return 1 << ARMII::S_BitShift;
995 }
996 return 0;
997 }
998
emitDataProcessingInstruction(const MachineInstr & MI,unsigned ImplicitRd,unsigned ImplicitRn)999 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1000 unsigned ImplicitRd,
1001 unsigned ImplicitRn) {
1002 const MCInstrDesc &MCID = MI.getDesc();
1003
1004 // Part of binary is determined by TableGn.
1005 unsigned Binary = getBinaryCodeForInstr(MI);
1006
1007 // Set the conditional execution predicate
1008 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1009
1010 // Encode S bit if MI modifies CPSR.
1011 Binary |= getAddrModeSBit(MI, MCID);
1012
1013 // Encode register def if there is one.
1014 unsigned NumDefs = MCID.getNumDefs();
1015 unsigned OpIdx = 0;
1016 if (NumDefs)
1017 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1018 else if (ImplicitRd)
1019 // Special handling for implicit use (e.g. PC).
1020 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1021
1022 if (MCID.Opcode == ARM::MOVi16) {
1023 // Get immediate from MI.
1024 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1025 ARM::reloc_arm_movw);
1026 // Encode imm which is the same as in emitMOVi32immInstruction().
1027 Binary |= Lo16 & 0xFFF;
1028 Binary |= ((Lo16 >> 12) & 0xF) << 16;
1029 emitWordLE(Binary);
1030 return;
1031 } else if(MCID.Opcode == ARM::MOVTi16) {
1032 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1033 ARM::reloc_arm_movt) >> 16);
1034 Binary |= Hi16 & 0xFFF;
1035 Binary |= ((Hi16 >> 12) & 0xF) << 16;
1036 emitWordLE(Binary);
1037 return;
1038 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1039 uint32_t v = ~MI.getOperand(2).getImm();
1040 int32_t lsb = CountTrailingZeros_32(v);
1041 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1042 // Instr{20-16} = msb, Instr{11-7} = lsb
1043 Binary |= (msb & 0x1F) << 16;
1044 Binary |= (lsb & 0x1F) << 7;
1045 emitWordLE(Binary);
1046 return;
1047 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1048 // Encode Rn in Instr{0-3}
1049 Binary |= getMachineOpValue(MI, OpIdx++);
1050
1051 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1052 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1053
1054 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1055 Binary |= (widthm1 & 0x1F) << 16;
1056 Binary |= (lsb & 0x1F) << 7;
1057 emitWordLE(Binary);
1058 return;
1059 }
1060
1061 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1062 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1063 ++OpIdx;
1064
1065 // Encode first non-shifter register operand if there is one.
1066 bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1067 if (!isUnary) {
1068 if (ImplicitRn)
1069 // Special handling for implicit use (e.g. PC).
1070 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1071 else {
1072 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1073 ++OpIdx;
1074 }
1075 }
1076
1077 // Encode shifter operand.
1078 const MachineOperand &MO = MI.getOperand(OpIdx);
1079 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1080 // Encode SoReg.
1081 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1082 return;
1083 }
1084
1085 if (MO.isReg()) {
1086 // Encode register Rm.
1087 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1088 return;
1089 }
1090
1091 // Encode so_imm.
1092 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1093
1094 emitWordLE(Binary);
1095 }
1096
emitLoadStoreInstruction(const MachineInstr & MI,unsigned ImplicitRd,unsigned ImplicitRn)1097 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1098 unsigned ImplicitRd,
1099 unsigned ImplicitRn) {
1100 const MCInstrDesc &MCID = MI.getDesc();
1101 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1102 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1103
1104 // Part of binary is determined by TableGn.
1105 unsigned Binary = getBinaryCodeForInstr(MI);
1106
1107 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1108 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1109 MI.getOpcode() == ARM::STRi12) {
1110 emitWordLE(Binary);
1111 return;
1112 }
1113
1114 // Set the conditional execution predicate
1115 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1116
1117 unsigned OpIdx = 0;
1118
1119 // Operand 0 of a pre- and post-indexed store is the address base
1120 // writeback. Skip it.
1121 bool Skipped = false;
1122 if (IsPrePost && Form == ARMII::StFrm) {
1123 ++OpIdx;
1124 Skipped = true;
1125 }
1126
1127 // Set first operand
1128 if (ImplicitRd)
1129 // Special handling for implicit use (e.g. PC).
1130 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1131 else
1132 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1133
1134 // Set second operand
1135 if (ImplicitRn)
1136 // Special handling for implicit use (e.g. PC).
1137 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1138 else
1139 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1140
1141 // If this is a two-address operand, skip it. e.g. LDR_PRE.
1142 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1143 ++OpIdx;
1144
1145 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1146 unsigned AM2Opc = (ImplicitRn == ARM::PC)
1147 ? 0 : MI.getOperand(OpIdx+1).getImm();
1148
1149 // Set bit U(23) according to sign of immed value (positive or negative).
1150 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1151 ARMII::U_BitShift);
1152 if (!MO2.getReg()) { // is immediate
1153 if (ARM_AM::getAM2Offset(AM2Opc))
1154 // Set the value of offset_12 field
1155 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1156 emitWordLE(Binary);
1157 return;
1158 }
1159
1160 // Set bit I(25), because this is not in immediate encoding.
1161 Binary |= 1 << ARMII::I_BitShift;
1162 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1163 // Set bit[3:0] to the corresponding Rm register
1164 Binary |= getARMRegisterNumbering(MO2.getReg());
1165
1166 // If this instr is in scaled register offset/index instruction, set
1167 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1168 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1169 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1170 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
1171 }
1172
1173 emitWordLE(Binary);
1174 }
1175
emitMiscLoadStoreInstruction(const MachineInstr & MI,unsigned ImplicitRn)1176 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1177 unsigned ImplicitRn) {
1178 const MCInstrDesc &MCID = MI.getDesc();
1179 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1180 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1181
1182 // Part of binary is determined by TableGn.
1183 unsigned Binary = getBinaryCodeForInstr(MI);
1184
1185 // Set the conditional execution predicate
1186 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1187
1188 unsigned OpIdx = 0;
1189
1190 // Operand 0 of a pre- and post-indexed store is the address base
1191 // writeback. Skip it.
1192 bool Skipped = false;
1193 if (IsPrePost && Form == ARMII::StMiscFrm) {
1194 ++OpIdx;
1195 Skipped = true;
1196 }
1197
1198 // Set first operand
1199 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1200
1201 // Skip LDRD and STRD's second operand.
1202 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1203 ++OpIdx;
1204
1205 // Set second operand
1206 if (ImplicitRn)
1207 // Special handling for implicit use (e.g. PC).
1208 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1209 else
1210 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1211
1212 // If this is a two-address operand, skip it. e.g. LDRH_POST.
1213 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1214 ++OpIdx;
1215
1216 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1217 unsigned AM3Opc = (ImplicitRn == ARM::PC)
1218 ? 0 : MI.getOperand(OpIdx+1).getImm();
1219
1220 // Set bit U(23) according to sign of immed value (positive or negative)
1221 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1222 ARMII::U_BitShift);
1223
1224 // If this instr is in register offset/index encoding, set bit[3:0]
1225 // to the corresponding Rm register.
1226 if (MO2.getReg()) {
1227 Binary |= getARMRegisterNumbering(MO2.getReg());
1228 emitWordLE(Binary);
1229 return;
1230 }
1231
1232 // This instr is in immediate offset/index encoding, set bit 22 to 1.
1233 Binary |= 1 << ARMII::AM3_I_BitShift;
1234 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1235 // Set operands
1236 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1237 Binary |= (ImmOffs & 0xF); // immedL
1238 }
1239
1240 emitWordLE(Binary);
1241 }
1242
getAddrModeUPBits(unsigned Mode)1243 static unsigned getAddrModeUPBits(unsigned Mode) {
1244 unsigned Binary = 0;
1245
1246 // Set addressing mode by modifying bits U(23) and P(24)
1247 // IA - Increment after - bit U = 1 and bit P = 0
1248 // IB - Increment before - bit U = 1 and bit P = 1
1249 // DA - Decrement after - bit U = 0 and bit P = 0
1250 // DB - Decrement before - bit U = 0 and bit P = 1
1251 switch (Mode) {
1252 default: llvm_unreachable("Unknown addressing sub-mode!");
1253 case ARM_AM::da: break;
1254 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1255 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1256 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1257 }
1258
1259 return Binary;
1260 }
1261
emitLoadStoreMultipleInstruction(const MachineInstr & MI)1262 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1263 const MCInstrDesc &MCID = MI.getDesc();
1264 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1265
1266 // Part of binary is determined by TableGn.
1267 unsigned Binary = getBinaryCodeForInstr(MI);
1268
1269 // Set the conditional execution predicate
1270 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1271
1272 // Skip operand 0 of an instruction with base register update.
1273 unsigned OpIdx = 0;
1274 if (IsUpdating)
1275 ++OpIdx;
1276
1277 // Set base address operand
1278 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1279
1280 // Set addressing mode by modifying bits U(23) and P(24)
1281 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1282 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1283
1284 // Set bit W(21)
1285 if (IsUpdating)
1286 Binary |= 0x1 << ARMII::W_BitShift;
1287
1288 // Set registers
1289 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1290 const MachineOperand &MO = MI.getOperand(i);
1291 if (!MO.isReg() || MO.isImplicit())
1292 break;
1293 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1294 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1295 RegNum < 16);
1296 Binary |= 0x1 << RegNum;
1297 }
1298
1299 emitWordLE(Binary);
1300 }
1301
emitMulFrmInstruction(const MachineInstr & MI)1302 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1303 const MCInstrDesc &MCID = MI.getDesc();
1304
1305 // Part of binary is determined by TableGn.
1306 unsigned Binary = getBinaryCodeForInstr(MI);
1307
1308 // Set the conditional execution predicate
1309 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1310
1311 // Encode S bit if MI modifies CPSR.
1312 Binary |= getAddrModeSBit(MI, MCID);
1313
1314 // 32x32->64bit operations have two destination registers. The number
1315 // of register definitions will tell us if that's what we're dealing with.
1316 unsigned OpIdx = 0;
1317 if (MCID.getNumDefs() == 2)
1318 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1319
1320 // Encode Rd
1321 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1322
1323 // Encode Rm
1324 Binary |= getMachineOpValue(MI, OpIdx++);
1325
1326 // Encode Rs
1327 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1328
1329 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1330 // it as Rn (for multiply, that's in the same offset as RdLo.
1331 if (MCID.getNumOperands() > OpIdx &&
1332 !MCID.OpInfo[OpIdx].isPredicate() &&
1333 !MCID.OpInfo[OpIdx].isOptionalDef())
1334 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1335
1336 emitWordLE(Binary);
1337 }
1338
emitExtendInstruction(const MachineInstr & MI)1339 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1340 const MCInstrDesc &MCID = MI.getDesc();
1341
1342 // Part of binary is determined by TableGn.
1343 unsigned Binary = getBinaryCodeForInstr(MI);
1344
1345 // Set the conditional execution predicate
1346 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1347
1348 unsigned OpIdx = 0;
1349
1350 // Encode Rd
1351 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1352
1353 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1354 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1355 if (MO2.isReg()) {
1356 // Two register operand form.
1357 // Encode Rn.
1358 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1359
1360 // Encode Rm.
1361 Binary |= getMachineOpValue(MI, MO2);
1362 ++OpIdx;
1363 } else {
1364 Binary |= getMachineOpValue(MI, MO1);
1365 }
1366
1367 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1368 if (MI.getOperand(OpIdx).isImm() &&
1369 !MCID.OpInfo[OpIdx].isPredicate() &&
1370 !MCID.OpInfo[OpIdx].isOptionalDef())
1371 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1372
1373 emitWordLE(Binary);
1374 }
1375
emitMiscArithInstruction(const MachineInstr & MI)1376 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1377 const MCInstrDesc &MCID = MI.getDesc();
1378
1379 // Part of binary is determined by TableGn.
1380 unsigned Binary = getBinaryCodeForInstr(MI);
1381
1382 // Set the conditional execution predicate
1383 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1384
1385 // PKH instructions are finished at this point
1386 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1387 emitWordLE(Binary);
1388 return;
1389 }
1390
1391 unsigned OpIdx = 0;
1392
1393 // Encode Rd
1394 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1395
1396 const MachineOperand &MO = MI.getOperand(OpIdx++);
1397 if (OpIdx == MCID.getNumOperands() ||
1398 MCID.OpInfo[OpIdx].isPredicate() ||
1399 MCID.OpInfo[OpIdx].isOptionalDef()) {
1400 // Encode Rm and it's done.
1401 Binary |= getMachineOpValue(MI, MO);
1402 emitWordLE(Binary);
1403 return;
1404 }
1405
1406 // Encode Rn.
1407 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1408
1409 // Encode Rm.
1410 Binary |= getMachineOpValue(MI, OpIdx++);
1411
1412 // Encode shift_imm.
1413 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1414 if (MCID.Opcode == ARM::PKHTB) {
1415 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1416 if (ShiftAmt == 32)
1417 ShiftAmt = 0;
1418 }
1419 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1420 Binary |= ShiftAmt << ARMII::ShiftShift;
1421
1422 emitWordLE(Binary);
1423 }
1424
emitSaturateInstruction(const MachineInstr & MI)1425 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1426 const MCInstrDesc &MCID = MI.getDesc();
1427
1428 // Part of binary is determined by TableGen.
1429 unsigned Binary = getBinaryCodeForInstr(MI);
1430
1431 // Set the conditional execution predicate
1432 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1433
1434 // Encode Rd
1435 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1436
1437 // Encode saturate bit position.
1438 unsigned Pos = MI.getOperand(1).getImm();
1439 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1440 Pos -= 1;
1441 assert((Pos < 16 || (Pos < 32 &&
1442 MCID.Opcode != ARM::SSAT16 &&
1443 MCID.Opcode != ARM::USAT16)) &&
1444 "saturate bit position out of range");
1445 Binary |= Pos << 16;
1446
1447 // Encode Rm
1448 Binary |= getMachineOpValue(MI, 2);
1449
1450 // Encode shift_imm.
1451 if (MCID.getNumOperands() == 4) {
1452 unsigned ShiftOp = MI.getOperand(3).getImm();
1453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1454 if (Opc == ARM_AM::asr)
1455 Binary |= (1 << 6);
1456 unsigned ShiftAmt = MI.getOperand(3).getImm();
1457 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1458 ShiftAmt = 0;
1459 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1460 Binary |= ShiftAmt << ARMII::ShiftShift;
1461 }
1462
1463 emitWordLE(Binary);
1464 }
1465
emitBranchInstruction(const MachineInstr & MI)1466 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1467 const MCInstrDesc &MCID = MI.getDesc();
1468
1469 if (MCID.Opcode == ARM::TPsoft) {
1470 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1471 }
1472
1473 // Part of binary is determined by TableGn.
1474 unsigned Binary = getBinaryCodeForInstr(MI);
1475
1476 // Set the conditional execution predicate
1477 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1478
1479 // Set signed_immed_24 field
1480 Binary |= getMachineOpValue(MI, 0);
1481
1482 emitWordLE(Binary);
1483 }
1484
emitInlineJumpTable(unsigned JTIndex)1485 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1486 // Remember the base address of the inline jump table.
1487 uintptr_t JTBase = MCE.getCurrentPCValue();
1488 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1489 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1490 << '\n');
1491
1492 // Now emit the jump table entries.
1493 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1494 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1495 if (IsPIC)
1496 // DestBB address - JT base.
1497 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1498 else
1499 // Absolute DestBB address.
1500 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1501 emitWordLE(0);
1502 }
1503 }
1504
emitMiscBranchInstruction(const MachineInstr & MI)1505 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1506 const MCInstrDesc &MCID = MI.getDesc();
1507
1508 // Handle jump tables.
1509 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1510 // First emit a ldr pc, [] instruction.
1511 emitDataProcessingInstruction(MI, ARM::PC);
1512
1513 // Then emit the inline jump table.
1514 unsigned JTIndex =
1515 (MCID.Opcode == ARM::BR_JTr)
1516 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1517 emitInlineJumpTable(JTIndex);
1518 return;
1519 } else if (MCID.Opcode == ARM::BR_JTm) {
1520 // First emit a ldr pc, [] instruction.
1521 emitLoadStoreInstruction(MI, ARM::PC);
1522
1523 // Then emit the inline jump table.
1524 emitInlineJumpTable(MI.getOperand(3).getIndex());
1525 return;
1526 }
1527
1528 // Part of binary is determined by TableGn.
1529 unsigned Binary = getBinaryCodeForInstr(MI);
1530
1531 // Set the conditional execution predicate
1532 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1533
1534 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1535 // The return register is LR.
1536 Binary |= getARMRegisterNumbering(ARM::LR);
1537 else
1538 // otherwise, set the return register
1539 Binary |= getMachineOpValue(MI, 0);
1540
1541 emitWordLE(Binary);
1542 }
1543
encodeVFPRd(const MachineInstr & MI,unsigned OpIdx)1544 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1545 unsigned RegD = MI.getOperand(OpIdx).getReg();
1546 unsigned Binary = 0;
1547 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1548 RegD = getARMRegisterNumbering(RegD);
1549 if (!isSPVFP)
1550 Binary |= RegD << ARMII::RegRdShift;
1551 else {
1552 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1553 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1554 }
1555 return Binary;
1556 }
1557
encodeVFPRn(const MachineInstr & MI,unsigned OpIdx)1558 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1559 unsigned RegN = MI.getOperand(OpIdx).getReg();
1560 unsigned Binary = 0;
1561 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1562 RegN = getARMRegisterNumbering(RegN);
1563 if (!isSPVFP)
1564 Binary |= RegN << ARMII::RegRnShift;
1565 else {
1566 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1567 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1568 }
1569 return Binary;
1570 }
1571
encodeVFPRm(const MachineInstr & MI,unsigned OpIdx)1572 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1573 unsigned RegM = MI.getOperand(OpIdx).getReg();
1574 unsigned Binary = 0;
1575 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1576 RegM = getARMRegisterNumbering(RegM);
1577 if (!isSPVFP)
1578 Binary |= RegM;
1579 else {
1580 Binary |= ((RegM & 0x1E) >> 1);
1581 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
1582 }
1583 return Binary;
1584 }
1585
emitVFPArithInstruction(const MachineInstr & MI)1586 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1587 const MCInstrDesc &MCID = MI.getDesc();
1588
1589 // Part of binary is determined by TableGn.
1590 unsigned Binary = getBinaryCodeForInstr(MI);
1591
1592 // Set the conditional execution predicate
1593 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1594
1595 unsigned OpIdx = 0;
1596 assert((Binary & ARMII::D_BitShift) == 0 &&
1597 (Binary & ARMII::N_BitShift) == 0 &&
1598 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1599
1600 // Encode Dd / Sd.
1601 Binary |= encodeVFPRd(MI, OpIdx++);
1602
1603 // If this is a two-address operand, skip it, e.g. FMACD.
1604 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1605 ++OpIdx;
1606
1607 // Encode Dn / Sn.
1608 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1609 Binary |= encodeVFPRn(MI, OpIdx++);
1610
1611 if (OpIdx == MCID.getNumOperands() ||
1612 MCID.OpInfo[OpIdx].isPredicate() ||
1613 MCID.OpInfo[OpIdx].isOptionalDef()) {
1614 // FCMPEZD etc. has only one operand.
1615 emitWordLE(Binary);
1616 return;
1617 }
1618
1619 // Encode Dm / Sm.
1620 Binary |= encodeVFPRm(MI, OpIdx);
1621
1622 emitWordLE(Binary);
1623 }
1624
emitVFPConversionInstruction(const MachineInstr & MI)1625 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1626 const MCInstrDesc &MCID = MI.getDesc();
1627 unsigned Form = MCID.TSFlags & ARMII::FormMask;
1628
1629 // Part of binary is determined by TableGn.
1630 unsigned Binary = getBinaryCodeForInstr(MI);
1631
1632 // Set the conditional execution predicate
1633 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1634
1635 switch (Form) {
1636 default: break;
1637 case ARMII::VFPConv1Frm:
1638 case ARMII::VFPConv2Frm:
1639 case ARMII::VFPConv3Frm:
1640 // Encode Dd / Sd.
1641 Binary |= encodeVFPRd(MI, 0);
1642 break;
1643 case ARMII::VFPConv4Frm:
1644 // Encode Dn / Sn.
1645 Binary |= encodeVFPRn(MI, 0);
1646 break;
1647 case ARMII::VFPConv5Frm:
1648 // Encode Dm / Sm.
1649 Binary |= encodeVFPRm(MI, 0);
1650 break;
1651 }
1652
1653 switch (Form) {
1654 default: break;
1655 case ARMII::VFPConv1Frm:
1656 // Encode Dm / Sm.
1657 Binary |= encodeVFPRm(MI, 1);
1658 break;
1659 case ARMII::VFPConv2Frm:
1660 case ARMII::VFPConv3Frm:
1661 // Encode Dn / Sn.
1662 Binary |= encodeVFPRn(MI, 1);
1663 break;
1664 case ARMII::VFPConv4Frm:
1665 case ARMII::VFPConv5Frm:
1666 // Encode Dd / Sd.
1667 Binary |= encodeVFPRd(MI, 1);
1668 break;
1669 }
1670
1671 if (Form == ARMII::VFPConv5Frm)
1672 // Encode Dn / Sn.
1673 Binary |= encodeVFPRn(MI, 2);
1674 else if (Form == ARMII::VFPConv3Frm)
1675 // Encode Dm / Sm.
1676 Binary |= encodeVFPRm(MI, 2);
1677
1678 emitWordLE(Binary);
1679 }
1680
emitVFPLoadStoreInstruction(const MachineInstr & MI)1681 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1682 // Part of binary is determined by TableGn.
1683 unsigned Binary = getBinaryCodeForInstr(MI);
1684
1685 // Set the conditional execution predicate
1686 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1687
1688 unsigned OpIdx = 0;
1689
1690 // Encode Dd / Sd.
1691 Binary |= encodeVFPRd(MI, OpIdx++);
1692
1693 // Encode address base.
1694 const MachineOperand &Base = MI.getOperand(OpIdx++);
1695 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1696
1697 // If there is a non-zero immediate offset, encode it.
1698 if (Base.isReg()) {
1699 const MachineOperand &Offset = MI.getOperand(OpIdx);
1700 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1701 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1702 Binary |= 1 << ARMII::U_BitShift;
1703 Binary |= ImmOffs;
1704 emitWordLE(Binary);
1705 return;
1706 }
1707 }
1708
1709 // If immediate offset is omitted, default to +0.
1710 Binary |= 1 << ARMII::U_BitShift;
1711
1712 emitWordLE(Binary);
1713 }
1714
1715 void
emitVFPLoadStoreMultipleInstruction(const MachineInstr & MI)1716 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1717 const MCInstrDesc &MCID = MI.getDesc();
1718 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1719
1720 // Part of binary is determined by TableGn.
1721 unsigned Binary = getBinaryCodeForInstr(MI);
1722
1723 // Set the conditional execution predicate
1724 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1725
1726 // Skip operand 0 of an instruction with base register update.
1727 unsigned OpIdx = 0;
1728 if (IsUpdating)
1729 ++OpIdx;
1730
1731 // Set base address operand
1732 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1733
1734 // Set addressing mode by modifying bits U(23) and P(24)
1735 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1736 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1737
1738 // Set bit W(21)
1739 if (IsUpdating)
1740 Binary |= 0x1 << ARMII::W_BitShift;
1741
1742 // First register is encoded in Dd.
1743 Binary |= encodeVFPRd(MI, OpIdx+2);
1744
1745 // Count the number of registers.
1746 unsigned NumRegs = 1;
1747 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1748 const MachineOperand &MO = MI.getOperand(i);
1749 if (!MO.isReg() || MO.isImplicit())
1750 break;
1751 ++NumRegs;
1752 }
1753 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1754 // Otherwise, it will be 0, in the case of 32-bit registers.
1755 if(Binary & 0x100)
1756 Binary |= NumRegs * 2;
1757 else
1758 Binary |= NumRegs;
1759
1760 emitWordLE(Binary);
1761 }
1762
encodeNEONRd(const MachineInstr & MI,unsigned OpIdx)1763 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1764 unsigned RegD = MI.getOperand(OpIdx).getReg();
1765 unsigned Binary = 0;
1766 RegD = getARMRegisterNumbering(RegD);
1767 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1768 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1769 return Binary;
1770 }
1771
encodeNEONRn(const MachineInstr & MI,unsigned OpIdx)1772 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1773 unsigned RegN = MI.getOperand(OpIdx).getReg();
1774 unsigned Binary = 0;
1775 RegN = getARMRegisterNumbering(RegN);
1776 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1777 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1778 return Binary;
1779 }
1780
encodeNEONRm(const MachineInstr & MI,unsigned OpIdx)1781 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1782 unsigned RegM = MI.getOperand(OpIdx).getReg();
1783 unsigned Binary = 0;
1784 RegM = getARMRegisterNumbering(RegM);
1785 Binary |= (RegM & 0xf);
1786 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1787 return Binary;
1788 }
1789
1790 /// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1791 /// data-processing instruction to the corresponding Thumb encoding.
convertNEONDataProcToThumb(unsigned Binary)1792 static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1793 assert((Binary & 0xfe000000) == 0xf2000000 &&
1794 "not an ARM NEON data-processing instruction");
1795 unsigned UBit = (Binary >> 24) & 1;
1796 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1797 }
1798
emitNEONLaneInstruction(const MachineInstr & MI)1799 void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1800 unsigned Binary = getBinaryCodeForInstr(MI);
1801
1802 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1803 const MCInstrDesc &MCID = MI.getDesc();
1804 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1805 RegTOpIdx = 0;
1806 RegNOpIdx = 1;
1807 LnOpIdx = 2;
1808 } else { // ARMII::NSetLnFrm
1809 RegTOpIdx = 2;
1810 RegNOpIdx = 0;
1811 LnOpIdx = 3;
1812 }
1813
1814 // Set the conditional execution predicate
1815 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1816
1817 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1818 RegT = getARMRegisterNumbering(RegT);
1819 Binary |= (RegT << ARMII::RegRdShift);
1820 Binary |= encodeNEONRn(MI, RegNOpIdx);
1821
1822 unsigned LaneShift;
1823 if ((Binary & (1 << 22)) != 0)
1824 LaneShift = 0; // 8-bit elements
1825 else if ((Binary & (1 << 5)) != 0)
1826 LaneShift = 1; // 16-bit elements
1827 else
1828 LaneShift = 2; // 32-bit elements
1829
1830 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1831 unsigned Opc1 = Lane >> 2;
1832 unsigned Opc2 = Lane & 3;
1833 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1834 Binary |= (Opc1 << 21);
1835 Binary |= (Opc2 << 5);
1836
1837 emitWordLE(Binary);
1838 }
1839
emitNEONDupInstruction(const MachineInstr & MI)1840 void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1841 unsigned Binary = getBinaryCodeForInstr(MI);
1842
1843 // Set the conditional execution predicate
1844 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1845
1846 unsigned RegT = MI.getOperand(1).getReg();
1847 RegT = getARMRegisterNumbering(RegT);
1848 Binary |= (RegT << ARMII::RegRdShift);
1849 Binary |= encodeNEONRn(MI, 0);
1850 emitWordLE(Binary);
1851 }
1852
emitNEON1RegModImmInstruction(const MachineInstr & MI)1853 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1854 unsigned Binary = getBinaryCodeForInstr(MI);
1855 // Destination register is encoded in Dd.
1856 Binary |= encodeNEONRd(MI, 0);
1857 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1858 unsigned Imm = MI.getOperand(1).getImm();
1859 unsigned Op = (Imm >> 12) & 1;
1860 unsigned Cmode = (Imm >> 8) & 0xf;
1861 unsigned I = (Imm >> 7) & 1;
1862 unsigned Imm3 = (Imm >> 4) & 0x7;
1863 unsigned Imm4 = Imm & 0xf;
1864 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1865 if (IsThumb)
1866 Binary = convertNEONDataProcToThumb(Binary);
1867 emitWordLE(Binary);
1868 }
1869
emitNEON2RegInstruction(const MachineInstr & MI)1870 void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1871 const MCInstrDesc &MCID = MI.getDesc();
1872 unsigned Binary = getBinaryCodeForInstr(MI);
1873 // Destination register is encoded in Dd; source register in Dm.
1874 unsigned OpIdx = 0;
1875 Binary |= encodeNEONRd(MI, OpIdx++);
1876 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1877 ++OpIdx;
1878 Binary |= encodeNEONRm(MI, OpIdx);
1879 if (IsThumb)
1880 Binary = convertNEONDataProcToThumb(Binary);
1881 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1882 emitWordLE(Binary);
1883 }
1884
emitNEON3RegInstruction(const MachineInstr & MI)1885 void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1886 const MCInstrDesc &MCID = MI.getDesc();
1887 unsigned Binary = getBinaryCodeForInstr(MI);
1888 // Destination register is encoded in Dd; source registers in Dn and Dm.
1889 unsigned OpIdx = 0;
1890 Binary |= encodeNEONRd(MI, OpIdx++);
1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1892 ++OpIdx;
1893 Binary |= encodeNEONRn(MI, OpIdx++);
1894 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1895 ++OpIdx;
1896 Binary |= encodeNEONRm(MI, OpIdx);
1897 if (IsThumb)
1898 Binary = convertNEONDataProcToThumb(Binary);
1899 // FIXME: This does not handle VMOVDneon or VMOVQ.
1900 emitWordLE(Binary);
1901 }
1902
1903 #include "ARMGenCodeEmitter.inc"
1904