/external/swiftshader/third_party/LLVM/lib/Target/ |
D | TargetRegisterInfo.cpp | 81 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | SIFormMemoryClauses.cpp | 311 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); in runOnMachineFunction() 312 MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count(); in runOnMachineFunction()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | VirtRegMap.cpp | 85 TRI->getAllocatableSet(mf, *I))); in runOnMachineFunction() 238 BitVector Allocatable = TRI->getAllocatableSet(*MF); in FindUnusedRegisters()
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D | RegisterScavenging.cpp | 335 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); in scavengeRegister()
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D | AggressiveAntiDepBreaker.cpp | 129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker() 532 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
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D | MachineSink.cpp | 221 AllocatableSet = TRI->getAllocatableSet(MF); in runOnMachineFunction()
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D | TargetInstrInfoImpl.cpp | 419 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); in isReallyTriviallyReMaterializableGeneric()
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D | MachineLICM.cpp | 322 AllocatableSet = TRI->getAllocatableSet(MF); in runOnMachineFunction()
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D | RegAllocLinearScan.cpp | 512 allocatableRegs_ = tri_->getAllocatableSet(fn); in runOnMachineFunction()
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/external/llvm/lib/Target/ARM/ |
D | Thumb1FrameLowering.cpp | 493 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp() 498 TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
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/external/swiftshader/third_party/LLVM/include/llvm/Target/ |
D | TargetRegisterInfo.h | 307 BitVector getAllocatableSet(const MachineFunction &MF,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsDelaySlotFiller.cpp | 337 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && in addLiveInRegs() 393 BitVector AllocSet = TRI.getAllocatableSet(MF); in setUnallocatableRegs()
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D | Mips16InstrInfo.cpp | 356 RI.getAllocatableSet in loadImmediate()
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/external/llvm/lib/Target/Mips/ |
D | MipsDelaySlotFiller.cpp | 309 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && in addLiveInRegs() 365 BitVector AllocSet = TRI.getAllocatableSet(MF); in setUnallocatableRegs()
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D | Mips16InstrInfo.cpp | 336 RI.getAllocatableSet in loadImmediate()
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/external/llvm/lib/CodeGen/ |
D | TargetRegisterInfo.cpp | 155 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
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D | RegisterScavenging.cpp | 355 BitVector Candidates = TRI->getAllocatableSet(MF, RC); in scavengeRegister()
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D | AggressiveAntiDepBreaker.cpp | 123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker() 518 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | AggressiveAntiDepBreaker.cpp | 135 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker() 537 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
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D | TargetRegisterInfo.cpp | 217 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
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D | RegisterScavenging.cpp | 541 BitVector Candidates = TRI->getAllocatableSet(MF, RC); in scavengeRegister()
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/external/llvm/include/llvm/Target/ |
D | TargetRegisterInfo.h | 354 BitVector getAllocatableSet(const MachineFunction &MF,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | Thumb1FrameLowering.cpp | 613 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp() 624 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | TargetRegisterInfo.h | 365 BitVector getAllocatableSet(const MachineFunction &MF,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
D | AVRExpandPseudoInsts.cpp | 872 TRI->getAllocatableSet in scavengeGPR8()
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