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Searched refs:getDef (Results 1 – 25 of 90) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenInstruction.cpp36 if (Init->getDef()->getName() != "outs") in CGIOperandList()
45 if (Init->getDef()->getName() != "ins") in CGIOperandList()
69 Record *Rec = Arg->getDef(); in CGIOperandList()
91 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops") in CGIOperandList()
444 return Constraint->getDef()->isSubClassOf("TypedOperand") && in isOperandAPointer()
445 Constraint->getDef()->getValueAsBit("IsPointer"); in isOperandAPointer()
466 Record *ResultRecord = ADI ? ADI->getDef() : nullptr; in tryAliasOpMatch()
468 if (ADI && ADI->getDef() == InstOpRec) { in tryAliasOpMatch()
483 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
484 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit(); in tryAliasOpMatch()
[all …]
DOptParserEmitter.cpp183 OS << getOptionName(*DI->getDef()); in EmitOptParser()
231 GroupFlags = DI->getDef()->getValueAsListInit("Flags"); in EmitOptParser()
232 OS << getOptionName(*DI->getDef()); in EmitOptParser()
239 OS << getOptionName(*DI->getDef()); in EmitOptParser()
264 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
268 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
DPseudoLoweringEmitter.cpp81 if (DI->getDef()->isSubClassOf("Register") || in addDagOperandMapping()
82 DI->getDef()->getName() == "zero_reg") { in addDagOperandMapping()
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping()
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
95 "Pseudo operand type '" + DI->getDef()->getName() + in addDagOperandMapping()
135 Record *Operator = OpDef->getDef(); in evaluateExpansion()
DRISCVCompressInstEmitter.cpp201 if (DI->getDef()->isSubClassOf("Register")) { in addDagOperandMapping()
203 if (!validateRegister(DI->getDef(), Inst.Operands[i].Rec)) in addDagOperandMapping()
206 "'Register: '" + DI->getDef()->getName() + in addDagOperandMapping()
210 OperandMap[i].Data.Reg = DI->getDef(); in addDagOperandMapping()
217 if (!validateTypes(DI->getDef(), Inst.Operands[i].Rec, IsSourceInst)) in addDagOperandMapping()
221 DI->getDef()->getName() + in addDagOperandMapping()
281 return Type1->getDef() == Type2->getDef(); in validateArgsTypes()
416 Record *Operator = OpDef->getDef(); in evaluateCompressPat()
433 Record *DestOperator = DestOpDef->getDef(); in evaluateCompressPat()
DRegisterBankEmitter.cpp60 const Record &getDef() const { return TheDef; } in getDef() function in __anon6b49e9f90111::RegisterBank
67 for (const auto &RCDef : getDef().getValueAsListOfDefs("RegisterClasses")) in getExplictlySpecifiedRegisterClasses()
308 PrintWarning(Bank.getDef().getLoc(), "Register bank names should be " in run()
311 PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here"); in run()
DCodeGenDAGPatterns.cpp1457 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef() in ApplyTypeConstraint()
1464 auto VVT = getValueTypeByHwMode(DI->getDef(), T.getHwModes()); in ApplyTypeConstraint()
1686 Op = DI->getDef(); in GetNumNodeResults()
1779 return ((DI->getDef() == NDI->getDef()) in isIsomorphicTo()
1839 cast<DefInit>(Val)->getDef()->getName() == "node")) { in SubstituteFormalArguments()
2119 Rec = DI->getDef(); in getComplexPatternInfo()
2136 if (DI && DI->getDef()->isSubClassOf("Operand")) { in getNumMIResults()
2137 DagInit *MIOps = DI->getDef()->getValueAsDag("MIOperandInfo"); in getNumMIResults()
2200 if (DI && DI->getDef()->isSubClassOf(Class)) in isOperandClass()
2234 MadeChange |= UpdateNodeType(i, getImplicitType(DI->getDef(), i, in ApplyTypeConstraints()
[all …]
DSearchableTableEmitter.cpp124 return Field.Enum->EntryMap[cast<DefInit>(I)->getDef()]->first; in primaryRepresentation()
131 return DI->getDef()->isSubClassOf("Intrinsic"); in isIntrinsic()
138 Intr = make_unique<CodeGenIntrinsic>(cast<DefInit>(I)->getDef()); in getIntrinsic()
235 Record *LHSr = cast<DefInit>(LHSI)->getDef(); in compareBy()
236 Record *RHSr = cast<DefInit>(RHSI)->getDef(); in compareBy()
251 auto LHSr = cast<DefInit>(LHSI)->getDef(); in compareBy()
252 auto RHSr = cast<DefInit>(RHSI)->getDef(); in compareBy()
523 Record *TypeRec = DI->getDef(); in parseFieldType()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp36 if (Init->getDef()->getName() != "outs") in CGIOperandList()
45 if (Init->getDef()->getName() != "ins") in CGIOperandList()
69 Record *Rec = Arg->getDef(); in CGIOperandList()
90 cast<DefInit>(MIOpInfo->getOperator())->getDef()->getName() != "ops") in CGIOperandList()
446 Record *ResultRecord = ADI ? ADI->getDef() : nullptr; in tryAliasOpMatch()
448 if (ADI && ADI->getDef() == InstOpRec) { in tryAliasOpMatch()
463 if (ADI && ADI->getDef()->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
464 ADI = ADI->getDef()->getValueAsDef("RegClass")->getDefInit(); in tryAliasOpMatch()
466 if (ADI && ADI->getDef()->isSubClassOf("RegisterClass")) { in tryAliasOpMatch()
470 .hasSubClass(&T.getRegisterClass(ADI->getDef()))) in tryAliasOpMatch()
[all …]
DOptParserEmitter.cpp181 OS << getOptionName(*DI->getDef()); in EmitOptParser()
226 GroupFlags = DI->getDef()->getValueAsListInit("Flags"); in EmitOptParser()
227 OS << getOptionName(*DI->getDef()); in EmitOptParser()
234 OS << getOptionName(*DI->getDef()); in EmitOptParser()
259 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
263 << cast<DefInit>(I)->getDef()->getName(); in EmitOptParser()
DPseudoLoweringEmitter.cpp81 if (DI->getDef()->isSubClassOf("Register") || in addDagOperandMapping()
82 DI->getDef()->getName() == "zero_reg") { in addDagOperandMapping()
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping()
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
95 "Pseudo operand type '" + DI->getDef()->getName() + in addDagOperandMapping()
135 Record *Operator = OpDef->getDef(); in evaluateExpansion()
DCodeGenDAGPatterns.cpp875 Record *Def = Pred->getDef(); in getPredicateCheck()
1024 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef() in ApplyTypeConstraint()
1030 getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()); in ApplyTypeConstraint()
1237 Op = DI->getDef(); in GetNumNodeResults()
1326 return ((DI->getDef() == NDI->getDef()) in isIsomorphicTo()
1385 cast<DefInit>(Val)->getDef()->getName() == "node")) { in SubstituteFormalArguments()
1603 Rec = DI->getDef(); in getComplexPatternInfo()
1620 if (DI && DI->getDef()->isSubClassOf("Operand")) { in getNumMIResults()
1621 DagInit *MIOps = DI->getDef()->getValueAsDag("MIOperandInfo"); in getNumMIResults()
1675 if (DI && DI->getDef()->isSubClassOf(Class)) in isOperandClass()
[all …]
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenInstruction.cpp36 if (Init->getDef()->getName() != "outs") in CGIOperandList()
45 if (Init->getDef()->getName() != "ins") in CGIOperandList()
67 Record *Rec = Arg->getDef(); in CGIOperandList()
85 ->getDef()->getName() != "ops") in CGIOperandList()
416 if (ADI && ADI->getDef() == InstOpRec) { in tryAliasOpMatch()
422 ResOp = ResultOperand(Result->getArgName(AliasOpNo), ADI->getDef()); in tryAliasOpMatch()
427 if (ADI && ADI->getDef()->isSubClassOf("Register")) { in tryAliasOpMatch()
432 InstOpRec = dynamic_cast<DefInit*>(DI->getArg(0))->getDef(); in tryAliasOpMatch()
442 .contains(T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
443 throw TGError(Loc, "fixed register " + ADI->getDef()->getName() + in tryAliasOpMatch()
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DPseudoLoweringEmitter.cpp34 if (DI->getDef()->isSubClassOf("Register") || in addDagOperandMapping()
35 DI->getDef()->getName() == "zero_reg") { in addDagOperandMapping()
37 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping()
46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) in addDagOperandMapping()
48 "Pseudo operand type '" + DI->getDef()->getName() + in addDagOperandMapping()
88 Record *Operator = OpDef->getDef(); in evaluateExpansion()
DSetTheory.cpp170 dynamic_cast<DefInit&>(*Expr->getOperator()).getDef()->getRecords(); in apply()
177 Record *Rec = Records.getDef(OS.str()); in apply()
228 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
230 Elts.insert(Def->getDef()); in evaluate()
245 Operator *Op = Operators.lookup(OpInit->getDef()->getName()); in evaluate()
DCodeGenDAGPatterns.cpp746 Record *Def = Pred->getDef(); in getPredicateCheck()
870 !static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef() in ApplyTypeConstraint()
874 getValueType(static_cast<DefInit*>(NodeToApply->getLeafValue())->getDef()); in ApplyTypeConstraint()
1027 Op = dynamic_cast<DefInit*>(Tree->getOperator())->getDef(); in GetNumNodeResults()
1103 return ((DI->getDef() == NDI->getDef()) in isIsomorphicTo()
1160 static_cast<DefInit*>(Val)->getDef()->getName() == "node") { in SubstituteFormalArguments()
1333 if (DI && DI->getDef()->isSubClassOf("ComplexPattern")) in getComplexPatternInfo()
1334 return &CGP.getComplexPattern(DI->getDef()); in getComplexPatternInfo()
1389 MadeChange |= UpdateNodeType(i, getImplicitType(DI->getDef(), i, in ApplyTypeConstraints()
1744 Record *R = DI->getDef(); in ParseTreePattern()
[all …]
DCodeGenRegisters.cpp103 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex")) in getSubRegs()
112 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) in getSubRegs()
116 SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef()); in getSubRegs()
124 SubRegs[BaseIdxInit->getDef()] = R2; in getSubRegs()
309 if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass")) in CodeGenRegisterClass()
317 if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex")) in CodeGenRegisterClass()
352 assert(!getDef() && "Only synthesized classes can inherit properties"); in inheritProperties()
503 if (!RegClasses[rci]->getDef()) in computeSubClasses()
576 if (Record *Def = RC->getDef()) in addToMaps()
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_nvc0.cpp76 bld.mkMovFromReg(i->getDef(0), i->op == OP_DIV ? 0 : 1); in handleDIV()
96 Value *src[2], *dst[2], *def = i->getDef(0); in handleRCPRSQ()
170 Value *dst64 = lo->getDef(0); in handleShift()
538 prev->setSrc(prev->srcCount(), useVec[i].tex->getDef(0)); in insertTextureBarriers()
544 bar->setSrc(bar->srcCount(), useVec[i].tex->getDef(0)); in insertTextureBarriers()
731 if (!i->getDef(0)->refCount()) in visit()
1178 bld.mkQuadop(0x00, tex->getDef(c), 0, tex->getDef(c), zero); in handleManualTXD()
1185 mov = bld.mkMov(def[c][l], tex->getDef(c)); in handleManualTXD()
1192 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c)); in handleManualTXD()
1326 bld.mkCvt(OP_CVT, TYPE_F32, i->getDef(def), type, i->getDef(def)); in handleTXLQ()
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Dnv50_ir_lowering_nv50.cpp180 bld->mkOp2(OP_UNION, mul->sType, mul->getDef(0), rr[5], rr[6]); in expandIntegerMUL()
182 bld->mkMov(mul->getDef(0), r[4]); in expandIntegerMUL()
185 bld->mkMov(mul->getDef(0), t[3]); in expandIntegerMUL()
415 i->getDef(0)->reg.size = 2; // $aX are only 16 bit in handleAddrDef()
448 arl = bld.mkOp2(OP_SHL, TYPE_U32, i->getDef(0), bld.getSSA(), bld.mkImm(0)); in handleAddrDef()
457 Value *def = mul->getDef(0); in handleMUL()
466 Value *res = cloneShallow(func, mul->getDef(0)); in handleMUL()
469 add->setSrc(0, mul->getDef(0)); in handleMUL()
586 if (insn->defExists(0) && insn->getDef(0)->reg.file == FILE_ADDRESS) in visit()
676 tid = bld.mkMov(bld.getScratch(), arg, TYPE_U32)->getDef(0); in visit()
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Dnv50_ir_peephole.cpp53 if (!getDef(0)->equals(getSrc(0))) in isNop()
74 if (getDef(d)->refCount() || getDef(d)->reg.data.id >= 0) in isDead()
110 if (mov->getDef(0)->reg.data.id < 0 && si && si->op != OP_PHI) { in visit()
273 if (ld->getDef(0)->refCount() == 0) in visit()
715 i->setSrc(1, bld.mkMov(bld.getSSA(type), i->getSrc(0), type)->getDef(0)); in expr()
866 mul2->def(0).replace(mul1->getDef(0), false); in tryCollapseChainedMULs()
873 mul2->def(0).replace(mul1->getDef(0), false); in tryCollapseChainedMULs()
881 if (mul2->getDef(0)->refCount() == 1 && !mul2->saturate) { in tryCollapseChainedMULs()
885 insn = (*mul2->getDef(0)->uses.begin())->getInsn(); in tryCollapseChainedMULs()
890 s2 = insn->getSrc(0) == mul1->getDef(0) ? 0 : 1; in tryCollapseChainedMULs()
[all …]
Dnv50_ir_ra.cpp469 LValue *tmp = new_LValue(func, phi->getDef(0)->asLValue()); in visit()
515 LValue *tmp = new_LValue(func, cal->getDef(d)->asLValue()); in visit()
521 mov->setDef(0, cal->getDef(d)); in visit()
599 bb->liveSet.clr(i->getDef(d)->id); in buildLiveSets()
605 bb->liveSet.clr(i->getDef(0)->id); in buildLiveSets()
654 bb->liveSet.clr(i->getDef(0)->id); in visit()
675 bb->liveSet.clr(i->getDef(d)->id); in visit()
676 if (i->getDef(d)->reg.data.id >= 0) // add hazard for fixed regs in visit()
677 i->getDef(d)->livei.extend(i->serial, i->serial); in visit()
1021 LValue *rep = (split ? insn->getSrc(0) : insn->getDef(0))->asLValue(); in makeCompound()
[all …]
Dnv50_ir_lowering_gm107.cpp181 bld.mkOp3(OP_SHFL, TYPE_F32, tex->getDef(c), tex->getDef(c), bld.mkImm(0), quad); in handleManualTXD()
188 mov = bld.mkMov(def[c][l], tex->getDef(c)); in handleManualTXD()
195 Instruction *u = bld.mkOp(OP_UNION, TYPE_U32, i->getDef(c)); in handleManualTXD()
231 insn->setSrc(0, shfl->getDef(0)); in handleDFDX()
/external/clang/utils/TableGen/
DClangSACheckersEmitter.cpp33 return isHidden(*DI->getDef()); in isHidden()
47 name = getPackageFullName(DI->getDef()); in getParentPackageFullName()
135 package = DI->getDef(); in EmitClangSACheckers()
156 Record *parentPackage = DI->getDef(); in EmitClangSACheckers()
162 recordGroupMap[DI->getDef()]->Checkers.insert(R); in EmitClangSACheckers()
169 addPackageToCheckerGroup(packages[i], DI->getDef(), recordGroupMap); in EmitClangSACheckers()
210 OS << groupToSortIndex[DI->getDef()] << ", "; in EmitClangSACheckers()
238 OS << groupToSortIndex[DI->getDef()] << ", "; in EmitClangSACheckers()
DClangDiagnosticsEmitter.cpp86 std::string CatName = getCategoryFromDiagGroup(Group->getDef(), in getDiagnosticCategory()
176 std::string GroupName = DI->getDef()->getValueAsString("GroupName"); in groupDiagnostics()
232 const Record *NextDiagGroup = GroupInit->getDef(); in groupDiagnostics()
263 const Record *NextDiagGroup = GroupInit->getDef(); in groupDiagnostics()
276 SrcMgr.PrintMessage(GroupInit->getDef()->getLoc().front(), in groupDiagnostics()
404 const Record *GroupRec = Group->getDef(); in compute()
423 if (groupInPedantic(Group->getDef())) in compute()
520 const Record *GroupRec = Group->getDef(); in EmitClangDiagsDefs()
552 DiagsInGroup.find(DI->getDef()->getValueAsString("GroupName")); in EmitClangDiagsDefs()
/external/llvm/lib/TableGen/
DSetTheory.cpp204 cast<DefInit>(Expr->getOperator())->getDef()->getRecords(); in apply()
215 Record *Rec = Records.getDef(OS.str()); in apply()
275 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
277 Elts.insert(Def->getDef()); in evaluate()
292 auto I = Operators.find(OpInit->getDef()->getName()); in evaluate()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/TableGen/
DSetTheory.cpp215 cast<DefInit>(Expr->getOperator())->getDef()->getRecords(); in apply()
226 Record *Rec = Records.getDef(OS.str()); in apply()
286 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
288 Elts.insert(Def->getDef()); in evaluate()
303 auto I = Operators.find(OpInit->getDef()->getName()); in evaluate()

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