| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2ISelLowering.cpp | 57 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
61 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
111 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 74 for (MCRegAliasIterator AI(ValAssign.getLocReg(), &TRI, true); in IsShadowAllocatedReg()
239 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
296 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? in LowerFormalArguments()
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState"); in LowerFormalArguments()
192 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg); in LowerFormalArguments()
244 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
269 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue()); in LowerReturn()
330 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
391 unsigned Reg = RV.getLocReg(); in LowerCall()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 84 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
85 MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); in lowerFormalArguments()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 117 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
163 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
164 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
344 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
387 assignValueToReg(NewRegs[0], VA.getLocReg(), VA); in assignCustomValue()
388 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA); in assignCustomValue()
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| D | ARMFastISel.cpp | 2003 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
2004 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2017 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
2018 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2020 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2021 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2067 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2068 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2070 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2071 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 242 MRI.addLiveIn(VA.getLocReg(), VRegs[OrigArgIdx]); in lowerFormalArguments()
243 MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); in lowerFormalArguments()
244 MIRBuilder.buildCopy(VRegs[OrigArgIdx], VA.getLocReg()); in lowerFormalArguments()
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| /external/llvm/lib/CodeGen/ |
| D | CallingConvLower.cpp | 222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
279 if (Loc1.getLocReg() != Loc2.getLocReg()) in resultsCompatible()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1636 VA.getLocReg()) in ProcessCallArgs()
1638 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1649 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1650 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1652 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1653 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
1692 .addReg(RVLocs[0].getLocReg()) in FinishCall()
1693 .addReg(RVLocs[1].getLocReg())); in FinishCall()
1695 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1696 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
420 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
435 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 251 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
258 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
345 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
353 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
357 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
421 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
[all …]
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 183 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
291 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
375 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
413 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 873 RegInfo.addLiveIn(VA.getLocReg(), VReg); in unpackFromRegLoc()
937 RegInfo.addLiveIn(VA.getLocReg(), LoVReg); in unpackF64OnRV32DSoftABI()
940 if (VA.getLocReg() == RISCV::X17) { in unpackF64OnRV32DSoftABI()
949 RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg); in unpackF64OnRV32DSoftABI()
1261 unsigned RegLo = VA.getLocReg(); in LowerCall()
1325 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
1414 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
1419 assert(VA.getLocReg() == ArgGPRs[0] && "Unexpected reg assignment"); in LowerCall()
1507 unsigned RegLo = VA.getLocReg(); in LowerReturn()
1518 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue); in LowerReturn()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments()
202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments()
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall()
483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); in LowerCall()
517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
600 unsigned Reg = RVLocs[i].getLocReg(); in LowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 241 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
349 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
437 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
442 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
475 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
382 DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), Glue); in lowerCallResult()
495 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCallArguments()
665 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
670 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 750 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) in X86SelectRet()
779 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
788 MRI.addLiveOut(VA.getLocReg()); in X86SelectRet()
1724 VA.getLocReg()).addReg(Arg); in DoSelectCall()
1725 RegArgs.push_back(VA.getLocReg()); in DoSelectCall()
1879 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
1880 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
1889 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
1890 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 331 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
429 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
528 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
595 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); in LowerReturn()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1977 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1978 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1990 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
1991 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
1993 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1994 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2040 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2041 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2043 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2044 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 742 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
849 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
897 ArgRegEnd = VA.getLocReg(); in LowerFormalArguments()
1028 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
1038 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
410 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
420 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
492 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
583 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 448 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
533 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
604 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
705 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1175 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1176 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1243 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1244 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1482 unsigned DestReg = VA.getLocReg(); in selectRet()
1517 RetRegs.push_back(VA.getLocReg()); in selectRet()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 139 Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); in handleAssignments()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 579 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
583 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
633 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
643 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
785 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1109 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1114 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1122 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1129 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1137 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
[all …]
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