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Searched refs:getNumNativeRegUnits (Results 1 – 4 of 4) sorted by relevance

/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
226 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
230 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
323 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
327 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
970 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { in runMCDesc()
1075 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " in runMCDesc()
1440 << " " << RegBank.getNumNativeRegUnits() << ",\n" in runTargetDesc()
DCodeGenRegisters.h642 unsigned getNumNativeRegUnits() const { in getNumNativeRegUnits() function
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp223 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
231 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
235 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
329 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() in EmitRegUnitPressure()
333 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); in EmitRegUnitPressure()
979 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { in runMCDesc()
1079 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " in runMCDesc()
1484 << " " << RegBank.getNumNativeRegUnits() << ",\n" in runTargetDesc()
DCodeGenRegisters.h689 unsigned getNumNativeRegUnits() const { in getNumNativeRegUnits() function