| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
165 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
188 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
224 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
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| D | AMDGPUDisassembler.h | 44 const char* getRegClassName(unsigned RegClassID) const;
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| /external/llvm/lib/CodeGen/ |
| D | LiveStackAnalysis.cpp | 84 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
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| D | RegAllocBase.cpp | 103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
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| D | VirtRegMap.cpp | 125 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
133 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
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| D | RegisterClassInfo.cpp | 143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
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| D | MachineVerifier.cpp | 983 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
1017 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1023 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1045 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
1046 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
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| D | RegisterScavenging.cpp | 429 TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) + in scavengeRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveStacks.cpp | 84 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
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| D | RegAllocBase.cpp | 107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
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| D | RegisterClassInfo.cpp | 155 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
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| D | VirtRegMap.cpp | 146 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
154 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
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| D | MachineVerifier.cpp | 1197 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
1267 << TRI->getRegClassName( in visitMachineOperand()
1280 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1286 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
1309 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
1310 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 104 OS << TRI->getRegClassName(&RC); in print()
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| D | RegisterBankInfo.cpp | 95 DEBUG(dbgs() << "Examine: " << TRI.getRegClassName(&CurRC) in addRegBankCoverage()
116 DEBUG(dbgs() << TRI.getRegClassName(TRI.getRegClass(SubRCId)) << ", "); in addRegBankCoverage()
152 DEBUG(dbgs() << TRI.getRegClassName(SubRC) << ", "); in addRegBankCoverage()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 111 OS << TRI->getRegClassName(&RC); in print()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 374 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
376 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
399 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
437 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
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| D | AMDGPUDisassembler.h | 60 const char* getRegClassName(unsigned RegClassID) const;
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 655 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
656 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 695 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
696 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 97 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 177 std::function<const char *(RegClass)> getRegClassName) { in filterTypeToRegisterSet() argument
210 RClass == getRegClassName(static_cast<RegClass>(TypeIndex))) { in filterTypeToRegisterSet()
247 Str << Indent << getRegClassName(static_cast<RegClass>(TypeIndex)) in filterTypeToRegisterSet()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 422 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 95 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 444 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
|