Home
last modified time | relevance | path

Searched refs:getRegNum (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceInstX8664.cpp95 const auto RegNum = Var->getRegNum(); in getRematerializableOffset()
166 assert(getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rsp || in emit()
167 getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rbp || in emit()
170 IceType_i32, Base->getRegNum())); in emit()
285 (getBase()->getRegNum() == Traits::RegisterSet::Reg_r15) || in toAsmAddress()
286 (getBase()->getRegNum() == Traits::RegisterSet::Reg_rsp) || in toAsmAddress()
287 (getBase()->getRegNum() == Traits::RegisterSet::Reg_rbp)); in toAsmAddress()
288 return X8664::Traits::Address(getEncodedGPR(getBase()->getRegNum()), in toAsmAddress()
289 getEncodedGPR(getIndex()->getRegNum()), in toAsmAddress()
295 return X8664::Traits::Address(getEncodedGPR(getBase()->getRegNum()), Disp, in toAsmAddress()
[all …]
DIceInstX86BaseImpl.h221 assert(Traits::getEncodedGPR(Eax->getRegNum()) == Encoded_rAX); in InstX86Cmpxchg()
233 assert(Edx->getRegNum() == RegisterSet::Reg_edx); in InstX86Cmpxchg8b()
234 assert(Eax->getRegNum() == RegisterSet::Reg_eax); in InstX86Cmpxchg8b()
235 assert(Ecx->getRegNum() == RegisterSet::Reg_ecx); in InstX86Cmpxchg8b()
236 assert(Ebx->getRegNum() == RegisterSet::Reg_ebx); in InstX86Cmpxchg8b()
592 Asm->jmp(Traits::getEncodedGPR(Var->getRegNum())); in emitIAS()
654 Asm->call(Traits::getEncodedGPR(Var->getRegNum())); in emitIAS()
713 GPRRegister VarReg = Traits::getEncodedGPR(Var->getRegNum()); in emitIASOpTyGPR()
737 GPRRegister VarReg = VarCanBeByte ? Traits::getEncodedGPR(Var->getRegNum()) in emitIASRegOpTyGPR()
738 : Traits::getEncodedGPR(Var->getRegNum()); in emitIASRegOpTyGPR()
[all …]
DIceInstX8632.cpp105 const auto RegNum = Var->getRegNum(); in getRematerializableOffset()
293 return X8632::Traits::Address(getEncodedGPR(getBase()->getRegNum()), in toAsmAddress()
294 getEncodedGPR(getIndex()->getRegNum()), in toAsmAddress()
298 return X8632::Traits::Address(getEncodedGPR(getBase()->getRegNum()), Disp, in toAsmAddress()
301 return X8632::Traits::Address(getEncodedGPR(getIndex()->getRegNum()), in toAsmAddress()
DIceCfgNode.cpp379 const auto RegNum1 = Var1->getRegNum(); in sameVarOrReg()
380 const auto RegNum2 = Var2->getRegNum(); in sameVarOrReg()
997 const auto RegNum = Var->getRegNum(); in emitRegisterUsage()
1008 return unsigned(V1->getRegNum()) < unsigned(V2->getRegNum()); in emitRegisterUsage()
1035 ++LiveRegCount[Dest->getRegNum()]; in emitLiveRangesEnded()
1040 SizeT NewCount = --LiveRegCount[Var->getRegNum()]; in emitLiveRangesEnded()
1132 ++LiveRegCount[Dest->getRegNum()]; in emit()
1134 --LiveRegCount[llvm::cast<Variable>(I.getSrc(0))->getRegNum()]; in emit()
1419 << Func->getTarget()->getRegName(Var->getRegNum(), in dump()
1445 << Func->getTarget()->getRegName(Var->getRegNum(), in dump()
DIceRegAlloc.cpp134 Var->setRegNumTmp(Var->getRegNum()); in initForGlobal()
261 Var->setRegNumTmp(Var->getRegNum()); in initForInfOnly()
313 Var->setRegNumTmp(Var->getRegNum()); in initForSecondChance()
604 *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp() in filterFreeWithPrecoloredRanges()
621 const auto RegNum = Cur->getRegNum(); in allocatePrecoloredRegister()
815 Str << (AssignedRegNum == Item->getRegNum() ? "Reassigning " in assignFinalRegisters()
846 PreDefinedRegisters[Var->getRegNum()] = true; in scan()
DIceTargetLoweringMIPS32.cpp1158 Str << '$' << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
1659 if (RegMIPS32::isFPRReg(Var->getRegNum())) in addProlog()
1663 auto *PhysicalRegister = makeReg(RegType, Var->getRegNum()); in addProlog()
1783 if (RegMIPS32::isFPRReg((*RIter)->getRegNum())) in addEpilog()
1787 auto *PhysicalRegister = makeReg(RegType, (*RIter)->getRegNum()); in addEpilog()
1855 IceType_f32, RegMIPS32::get64PairFirstRegNum(SrcV->getRegNum())); in legalizeMovFp()
1858 IceType_f32, RegMIPS32::get64PairSecondRegNum(SrcV->getRegNum())); in legalizeMovFp()
1888 const bool IsDstGPR = RegMIPS32::isGPRReg(Dest->getRegNum()); in legalizeMov()
1889 const bool IsSrcGPR = RegMIPS32::isGPRReg(SrcR->getRegNum()); in legalizeMov()
1890 const RegNumT SRegNum = SrcR->getRegNum(); in legalizeMov()
[all …]
DIceInstARM32.cpp1368 const auto Base = BaseReg->getRegNum(); in emitSRegsAsText()
1396 return RegNumT::fixme(Before->getRegNum() + 1) == After->getRegNum(); in isAssignedConsecutiveRegisters()
1416 RegARM32::getEncodedGPR(Var->getRegNum()); in emitUsingForm()
1567 const auto SrcReg = Src->getRegNum(); in getDRegister()
1624 const auto SrcReg = Src->getRegNum(); in getSRegister()
1755 Asm->vmovqir(Dest->asType(Func, DestTy, Dest->getRegNum()), in emitIAS()
1757 Src->asType(Func, SrcTy, Src->getRegNum()), getPredicate()); in emitIAS()
2723 assert(LR->getRegNum() == RegARM32::Reg_lr); in emit()
DIceTargetLoweringX8664.cpp324 const auto RegNum = Var->getRegNum(); in isAssignedToRspOrRbp()
442 RegNum = Traits::getGprForType(IceType_i64, T->getRegNum()); in _sandbox_mem_reference()
DIceTargetLoweringARM32.cpp407 RegNumT::fixme(RegARM32::getI64PairFirstGPRNum(Var->getRegNum())); in copyRegAllocFromInfWeightVariable64On32()
1237 Str << getRegName(Var->getRegNum(), Var->getType()); in emitVariable()
1786 Base->getRegNum() == Target->getFrameOrStackReg(); in newBaseRegister()
1843 assert(TempBaseReg->getRegNum() == Target->getReservedTmpReg()); in resetTempBaseIfClobberedBy()
1848 Dest->getRegNum() == TempBaseReg->getRegNum()) { in resetTempBaseIfClobberedBy()
1893 const int32_t ExtraOffset = (Var->getRegNum() == Target->getFrameReg()) in legalizeMov()
1898 Variable *Base = Target->getPhysicalRegister(Var->getRegNum()); in legalizeMov()
1899 Variable *T = newBaseRegister(Base, Offset, Dest->getRegNum()); in legalizeMov()
1965 const int32_t ExtraOffset = (Base->getRegNum() == Target->getFrameReg()) in legalizeMemOperand()
1969 Base = Target->getPhysicalRegister(Base->getRegNum()); in legalizeMemOperand()
[all …]
DIceCfg.cpp1133 Src0Var->getRegNum(), Src0Var->getStackOffset() + Src1Imm->getValue()); in rematerializeArithmetic()
1149 Instr->getDest()->setRematerializable(Src0Var->getRegNum(), in rematerializeAssign()
1170 Dest->setRematerializable(Src0Var->getRegNum(), Src0Var->getStackOffset()); in rematerializeCast()
DIceOperand.h764 bool hasReg() const { return getRegNum().hasValue(); } in hasReg()
765 RegNumT getRegNum() const { return RegNum; } in getRegNum() function
DIceInst.cpp1098 if (Dest->hasReg() && Dest->getRegNum() == SrcVar->getRegNum()) { in checkForRedundantAssign()
DIceInstMIPS32.cpp430 assert(RA->getRegNum() == RegMIPS32::Reg_RA); in emit()
613 assert(RA->getRegNum() == RegMIPS32::Reg_RA); in emitIAS()
DIceAssemblerMIPS32.cpp127 const auto Reg = Var->getRegNum(); in getEncodedGPRegNum()
133 const auto Reg = Var->getRegNum(); in getEncodedFPRegNum()
DIceAssemblerARM32.cpp180 const auto Reg = Var->getRegNum(); in getEncodedGPRegNum()
187 return RegARM32::getEncodedSReg(Var->getRegNum()); in getEncodedSRegNum()
191 return RegARM32::getEncodedDReg(Var->getRegNum()); in getEncodedDRegNum()
195 return RegARM32::getEncodedQReg(Var->getRegNum()); in getEncodedQRegNum()
DIceTargetLowering.cpp821 RegsUsed[Var->getRegNum()] = true; in getVarStackSlotParams()
DIceInstX86Base.h673 MemOp->getBase()->getRegNum() == this->getDest()->getRegNum() && in deoptLeaToAddOrNull()
1100 const auto SrcReg = SrcVar->getRegNum(); in isRedundantAssign()
1101 const auto DestReg = this->Dest->getRegNum(); in isRedundantAssign()
DIceTargetLoweringARM32.h1187 TempBaseReg->getRegNum() == Target->getReservedTmpReg()); in assertNoTempOrAssignedToIP()
DIceTargetLoweringX86BaseImpl.h954 Str << "%" << getRegName(Var->getRegNum(), VarType);
5957 if (Var->getRegNum() == getStackReg())
6737 SrcLegal = legalize(Src, Legal_Reg, Dest->getRegNum());
7760 assert(Slot->getRegNum().hasNoValue());
8010 (RegNum.hasValue() && RegNum != Var->getRegNum())) {
DIceTargetLoweringX86Base.h198 const std::string RegName = Traits::getRegName(Dest->getRegNum()); in createGetIPForRegister()