| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 138 unsigned getRegPressureSetLimit(unsigned Idx) const { in getRegPressureSetLimit() function
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| D | TargetRegisterInfo.h | 776 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 134 unsigned getRegPressureSetLimit(unsigned Idx) const { in getRegPressureSetLimit() function
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 51 unsigned getRegPressureSetLimit(const MachineFunction &MF,
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| D | SIRegisterInfo.cpp | 212 unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF, in getRegPressureSetLimit() function in SIRegisterInfo
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| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 179 return TRI->getRegPressureSetLimit(*MF, Idx) - in computePSetLimit()
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| D | RegisterPressure.cpp | 930 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
1130 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
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| D | MachineLICM.cpp | 290 RegLimit[i] = TRI->getRegPressureSetLimit(MF, i); in runOnMachineFunction()
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| D | MachineScheduler.cpp | 945 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
977 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 190 return TRI->getRegPressureSetLimit(*MF, Idx) - in computePSetLimit()
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| D | RegisterPressure.cpp | 951 unsigned Limit = RCI->getRegPressureSetLimit(i); in computeExcessPressureDelta()
1151 unsigned Limit = RCI->getRegPressureSetLimit(PSetID); in getUpwardPressureDelta()
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| D | MachineLICM.cpp | 334 RegLimit[i] = TRI->getRegPressureSetLimit(MF, i); in runOnMachineFunction()
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| D | MachineScheduler.cpp | 1063 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); in initRegPressure()
1093 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID); in updateScheduledPressure()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 220 unsigned getRegPressureSetLimit(const MachineFunction &MF,
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| D | GCNSchedStrategy.cpp | 52 SGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
54 VGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
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| D | SIRegisterInfo.cpp | 1550 unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF, in getRegPressureSetLimit() function in SIRegisterInfo
1560 return AMDGPURegisterInfo::getRegPressureSetLimit(MF, Idx); in getRegPressureSetLimit()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 733 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 279 unsigned Limit = DAG->getRegClassInfo()->getRegPressureSetLimit(i); in initialize()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 3737 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
7212 getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 3884 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
7625 getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 3307 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
13592 getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 4988 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
19158 getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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