| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 307 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
315 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
323 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
332 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
341 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
461 unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg, in getRegSizeInBits() function in TargetRegisterInfo
480 return getRegSizeInBits(*RC); in getRegSizeInBits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 136 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
143 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
150 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
157 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
170 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
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| D | X86CallLowering.cpp | 138 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
260 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
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| D | X86FlagsCopyLowering.cpp | 860 Inverted ? X86::COND_E : X86::COND_NE, TRI->getRegSizeInBits(CMovRC) / 8, in rewriteCMov()
935 int OrigRegSize = TRI->getRegSizeInBits(OrigRC) / 8; in rewriteSetCarryExtended()
936 int TargetRegSize = TRI->getRegSizeInBits(SetBRC) / 8; in rewriteSetCarryExtended()
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| D | X86SpeculativeLoadHardening.cpp | 741 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCFG()
1676 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1); in extractPredStateFromSP()
1968 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister()
2013 int Bytes = TRI->getRegSizeInBits(*RC) / 8; in hardenValueInRegister()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 41 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 258 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
265 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 692 getSpillEltSize(getRegSizeInBits(*RC) / 8, true); in spillSGPR()
863 getSpillEltSize(getRegSizeInBits(*RC) / 8, false); in restoreSGPR()
1255 unsigned Size = getRegSizeInBits(*RC); in hasVGPRs()
1278 switch (getRegSizeInBits(*SRC)) { in getEquivalentVGPRClass()
1298 switch (getRegSizeInBits(*VRC)) { in getEquivalentSGPRClass()
1518 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
1519 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
1520 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
1579 unsigned Size = getRegSizeInBits(MO.getReg(), MRI); in getConstrainedRegClassForOperand()
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| D | GCNRegPressure.cpp | 91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : in getRegKind()
92 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
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| D | SIInstrInfo.h | 716 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; in getOpSize()
722 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
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| D | SIInstrInfo.cpp | 302 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOpBaseRegImmOfs()
306 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOpBaseRegImmOfs()
453 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold; in shouldClusterMemOps()
563 if (RI.getRegSizeInBits(*RC) > 32) { in copyPhysReg()
655 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
811 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
813 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
815 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
1836 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
3404 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
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| D | InstructionSelect.cpp | 203 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) { in runOnMachineFunction()
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| D | RegisterBankInfo.cpp | 469 return TRI.getRegSizeInBits(*RC); in getSizeInBits()
471 return TRI.getRegSizeInBits(Reg, MRI); in getSizeInBits()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 121 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in storeRegToStackSlot()
148 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in loadRegFromStackSlot()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 116 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
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| D | AVRFrameLowering.cpp | 254 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
292 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 817 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
818 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 139 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
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| D | HexagonBitTracker.cpp | 119 return TRI.getRegSizeInBits(RC); in getPhysRegBitWidth()
122 return TRI.getRegSizeInBits(*RC); in getPhysRegBitWidth()
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| D | BitTracker.cpp | 341 return TRI.getRegSizeInBits(VC); in getRegBitWidth()
717 return TRI.getRegSizeInBits(PC); in getPhysRegBitWidth()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 314 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() function
763 unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 292 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
293 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()
294 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()
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| D | MipsSEInstrInfo.cpp | 700 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); in compareOpndSize()
701 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); in compareOpndSize()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 124 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg()
|