| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/tools/llvm-exegesis/X86/ |
| D | AnalysisTest.cpp | 31 const auto &SM = STI->getSchedModel(); in AnalysisTest()
74 computeIdealizedProcResPressure(STI->getSchedModel(), {{P0Idx, 2}}); in TEST_F()
80 computeIdealizedProcResPressure(STI->getSchedModel(), {{P05Idx, 2}}); in TEST_F()
87 STI->getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}}); in TEST_F()
95 STI->getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}}); in TEST_F()
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | RegisterFileStatistics.cpp | 23 const MCSchedModel &SM = STI.getSchedModel(); in initializeRegisterFileInfo()
80 assert(STI.getSchedModel().hasExtraProcessorInfo() && in printView()
83 STI.getSchedModel().getExtraProcessorInfo(); in printView()
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| D | ResourcePressureView.cpp | 26 const MCSchedModel &SM = STI.getSchedModel(); in initialize()
101 const MCSchedModel &SM = STI.getSchedModel(); in printResourcePressurePerIteration()
144 printColumnNames(FOS, STI.getSchedModel()); in printResourcePressurePerInstruction()
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| D | InstrBuilder.h | 66 ProcResourceMasks(STI.getSchedModel().getNumProcResourceKinds()) { in InstrBuilder()
67 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); in InstrBuilder()
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| D | InstrBuilder.cpp | 33 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
161 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
319 assert(STI.getSchedModel().hasInstrSchedModel() && in createInstrDescImpl()
325 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
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| D | llvm-mca.cpp | 403 if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) { in main()
409 if (!STI->getSchedModel().hasInstrSchedModel()) { in main()
415 if (STI->getSchedModel().InstrItineraries) in main()
457 const MCSchedModel &SM = STI->getSchedModel(); in main()
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| D | SchedulerStatistics.h | 68 : SM(STI.getSchedModel()), NumIssued(0), NumCycles(0) {} in SchedulerStatistics()
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| D | Context.cpp | 34 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
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| D | InstructionInfoView.cpp | 24 const MCSchedModel &SM = STI.getSchedModel(); in printView()
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| D | DispatchStage.cpp | 80 const MCSchedModel &SM = STI.getSchedModel(); in updateRAWDependencies()
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
| D | Analysis.cpp | 133 const auto &SchedModel = SubtargetInfo_->getSchedModel(); in printInstructionRowCsv()
333 const auto &SM = STI.getSchedModel(); in getNonRedundantWriteProcRes()
380 STI.getSchedModel(), NonRedundantWriteProcRes)) {} in SchedClass()
458 const auto &SM = SubtargetInfo_->getSchedModel(); in printSchedClassDescHtml()
489 writeEscaped<kEscapeHtml>(OS, SubtargetInfo_->getSchedModel() in printSchedClassDescHtml()
586 const auto &SchedModel = SubtargetInfo_->getSchedModel(); in run()
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| D | Latency.cpp | 98 if (!State.getSubtargetInfo().getSchedModel().hasExtraProcessorInfo()) in getCounterName()
101 .getSchedModel() in getCounterName()
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| D | Uops.cpp | 203 const auto &SchedModel = State.getSubtargetInfo().getSchedModel(); in runMeasurements()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.cpp | 291 return getSchedModel().isOutOfOrder() && isSwift(); in enableMachineScheduler()
298 if (getSchedModel().isOutOfOrder() && isSwift()) in enablePostRAScheduler()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 204 SchedModel = DAG->getSchedModel(); in initialize()
211 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
221 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
222 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
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| /external/llvm/lib/Target/ |
| D | TargetSubtargetInfo.cpp | 49 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetSubtargetInfo.cpp | 63 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 255 SchedModel = DAG->getSchedModel(); in initialize()
262 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
272 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
273 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 125 SchedModel.init(ST.getSchedModel(), &ST, TII); in runOnMachineFunction()
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| /external/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 115 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
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| /external/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 108 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 116 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 92 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
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| D | MCSubtargetInfo.cpp | 118 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 243 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel() function
|