Searched refs:getStackPtrOffsetReg (Results 1 – 5 of 5) sorted by relevance
163 assert(MFI->getStackPtrOffsetReg() == AMDGPU::SP_REG); in getReservedPrivateSegmentWaveByteOffsetReg()167 unsigned SPReg = MFI->getStackPtrOffsetReg(); in getReservedPrivateSegmentWaveByteOffsetReg()254 unsigned SPReg = MFI->getStackPtrOffsetReg(); in emitEntryFunctionPrologue()544 unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg(); in emitPrologue()623 unsigned StackPtrReg = FuncInfo->getStackPtrOffsetReg(); in emitEpilogue()742 SavedRegs.reset(MFI->getStackPtrOffsetReg()); in determineCalleeSaves()767 unsigned SPReg = MFI->getStackPtrOffsetReg(); in eliminateCallFramePseudoInstr()
441 unsigned getStackPtrOffsetReg() const { in getStackPtrOffsetReg() function
212 unsigned StackPtrReg = MFI->getStackPtrOffsetReg(); in getReservedRegs()668 assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() && in spillSGPR()
1141 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg(); in SelectMUBUFScratchOffen()1202 Info->getStackPtrOffsetReg() : Info->getScratchWaveOffsetReg(); in SelectMUBUFScratchOffset()
3428 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine) in EmitInstrWithCustomInserter()3429 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit) in EmitInstrWithCustomInserter()8425 assert(Info->getStackPtrOffsetReg() != Info->getFrameOffsetReg()); in finalizeLowering()8427 Info->getStackPtrOffsetReg())); in finalizeLowering()8428 MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg()); in finalizeLowering()