| /external/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 190 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead()
254 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
255 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86FixupBWInsts.cpp | 181 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead()
310 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != in tryReplaceCopy()
311 TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) in tryReplaceCopy()
|
| D | X86InstructionSelector.cpp | 203 static unsigned getSubRegIndex(const TargetRegisterClass *RC) { in getSubRegIndex() function
259 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
288 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
912 .addImm(getSubRegIndex(SrcRC)); in selectAnyext()
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece()
138 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); in AddMachineRegPiece()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 183 LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); in aliasRM()
229 if (unsigned Idx = TRI.getSubRegIndex(R, RR.Reg)) in mapTo()
231 if (unsigned Idx = TRI.getSubRegIndex(RR.Reg, R)) { in mapTo()
|
| D | HexagonBlockRanges.cpp | 246 unsigned SI = S.getSubRegIndex(); in getLiveIns()
286 SRs.insert({R.Reg, I.getSubRegIndex()}); in expandToSubRegs()
|
| D | RDFCopy.cpp | 128 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy()
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 109 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in addMachineReg()
132 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); in addMachineReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCQPXLoadSplat.cpp | 109 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg()); in runOnMachineFunction()
|
| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex() function in MCRegisterInfo
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCQPXLoadSplat.cpp | 109 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg()); in runOnMachineFunction()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 353 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
497 unsigned getSubRegIndex() const { in getSubRegIndex() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 363 unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
521 unsigned getSubRegIndex() const { in getSubRegIndex() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 43 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex() function in MCRegisterInfo
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 207 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy()
208 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
|
| D | LivePhysRegs.cpp | 169 unsigned SI = S.getSubRegIndex(); in addBlockLiveIns()
|
| D | StackMaps.cpp | 160 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 400 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); in computeSubRegs()
485 if (Cand == this || getSubRegIndex(Cand)) in computeSecondarySubRegs()
496 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); in computeSecondarySubRegs()
498 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs()
537 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs()
1340 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
|
| D | CodeGenRegisters.h | 193 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { in getSubRegIndex() function
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 378 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 347 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); in computeSubRegs()
423 if (Cand == this || getSubRegIndex(Cand)) in computeSecondarySubRegs()
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j])) in computeSecondarySubRegs()
469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs()
1145 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); in computeComposites()
|
| D | CodeGenRegisters.h | 167 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { in getSubRegIndex() function
|
| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 224 unsigned getSubRegIndex(StringRef Name);
879 SubReg = getSubRegIndex(Name); in parseSubRegisterIndex()
1247 unsigned SubRegIndex = getSubRegIndex(Token.stringValue()); in parseSubRegisterIndexOperand()
1918 unsigned MIParser::getSubRegIndex(StringRef Name) { in getSubRegIndex() function in MIParser
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 277 SRs.insert({R.Reg, I.getSubRegIndex()}); in expandToSubRegs()
|