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Searched refs:getTRI (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp245 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in hasAliasOf()
260 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in hasCoverOf()
275 for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { in insert()
326 for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R) in makeRegRef()
327 for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S) in makeRegRef()
335 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef()
342 BitVector AR(PRI.getTRI().getNumRegs()); in makeRegRef()
357 for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) { in makeRegRef()
368 OS << ' ' << printRegUnit(U, &PRI.getTRI()); in print()
DRDFRegisters.h133 const TargetRegisterInfo &getTRI() const { return TRI; } in getTRI() function
160 : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} in RegisterAggr()
DRDFCopy.cpp51 const TargetRegisterInfo &TRI = DFG.getTRI(); in interpretAsCopy()
123 const TargetRegisterInfo &TRI = DFG.getTRI(); in run()
DRDFLiveness.h56 : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()), in Liveness()
DRDFDeadCode.cpp71 for (unsigned R = 0, RN = DFG.getTRI().getNumRegs(); R != RN; ++R) { in isLiveInstr()
DRDFGraph.h664 const TargetRegisterInfo &getTRI() const { return TRI; } in getTRI() function
DRDFLiveness.cpp65 OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{'; in operator <<()
DRDFGraph.cpp60 auto &TRI = P.G.getTRI(); in operator <<()
/external/llvm/lib/Target/Hexagon/
DRDFCopy.cpp46 const TargetRegisterInfo &TRI = DFG.getTRI(); in interpretAsCopy()
65 unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx); in interpretAsCopy()
DRDFLiveness.h37 : DFG(g), TRI(g.getTRI()), MDT(g.getDT()), MDF(g.getDF()), in Liveness()
DRDFGraph.h621 const TargetRegisterInfo &getTRI() const { in getTRI() function
DRDFGraph.cpp33 auto &TRI = P.G.getTRI(); in operator <<()
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.cpp571 dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
575 dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
1476 dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' '; in pickBlock()
1599 DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0); in checkRegUsageImpact()
DSIMachineScheduler.h452 const TargetRegisterInfo *getTRI() { return TRI; } in getTRI() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h461 const TargetRegisterInfo *getTRI() { return TRI; } in getTRI() function
DSIMachineScheduler.cpp605 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
609 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in printDebug()
1638 << printVRegOrUnit(Reg, DAG->getTRI()) << ' '; in pickBlock()
1752 DiffSetPressure.assign(DAG->getTRI()->getNumRegPressureSets(), 0); in checkRegUsageImpact()