1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2007 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 */ 8 #ifndef __ASM_ARM_ARCH_CLK_H__ 9 #define __ASM_ARM_ARCH_CLK_H__ 10 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/at91_pmc.h> 13 #include <asm/global_data.h> 14 15 #define GCK_CSS_SLOW_CLK 0 16 #define GCK_CSS_MAIN_CLK 1 17 #define GCK_CSS_PLLA_CLK 2 18 #define GCK_CSS_UPLL_CLK 3 19 #define GCK_CSS_MCK_CLK 4 20 #define GCK_CSS_AUDIO_CLK 5 21 22 #define AT91_UTMI_PLL_CLK_FREQ 480000000 23 get_cpu_clk_rate(void)24static inline unsigned long get_cpu_clk_rate(void) 25 { 26 DECLARE_GLOBAL_DATA_PTR; 27 return gd->arch.cpu_clk_rate_hz; 28 } 29 get_main_clk_rate(void)30static inline unsigned long get_main_clk_rate(void) 31 { 32 DECLARE_GLOBAL_DATA_PTR; 33 return gd->arch.main_clk_rate_hz; 34 } 35 get_mck_clk_rate(void)36static inline unsigned long get_mck_clk_rate(void) 37 { 38 DECLARE_GLOBAL_DATA_PTR; 39 return gd->arch.mck_rate_hz; 40 } 41 get_plla_clk_rate(void)42static inline unsigned long get_plla_clk_rate(void) 43 { 44 DECLARE_GLOBAL_DATA_PTR; 45 return gd->arch.plla_rate_hz; 46 } 47 get_pllb_clk_rate(void)48static inline unsigned long get_pllb_clk_rate(void) 49 { 50 DECLARE_GLOBAL_DATA_PTR; 51 return gd->arch.pllb_rate_hz; 52 } 53 get_pllb_init(void)54static inline u32 get_pllb_init(void) 55 { 56 DECLARE_GLOBAL_DATA_PTR; 57 return gd->arch.at91_pllb_usb_init; 58 } 59 60 #ifdef CPU_HAS_H32MXDIV get_h32mxdiv(void)61static inline unsigned int get_h32mxdiv(void) 62 { 63 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 64 65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; 66 } 67 #else get_h32mxdiv(void)68static inline unsigned int get_h32mxdiv(void) 69 { 70 return 0; 71 } 72 #endif 73 get_macb_pclk_rate(unsigned int dev_id)74static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) 75 { 76 if (get_h32mxdiv()) 77 return get_mck_clk_rate() / 2; 78 else 79 return get_mck_clk_rate(); 80 } 81 get_usart_clk_rate(unsigned int dev_id)82static inline unsigned long get_usart_clk_rate(unsigned int dev_id) 83 { 84 if (get_h32mxdiv()) 85 return get_mck_clk_rate() / 2; 86 else 87 return get_mck_clk_rate(); 88 } 89 get_lcdc_clk_rate(unsigned int dev_id)90static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) 91 { 92 return get_mck_clk_rate(); 93 } 94 get_spi_clk_rate(unsigned int dev_id)95static inline unsigned long get_spi_clk_rate(unsigned int dev_id) 96 { 97 if (get_h32mxdiv()) 98 return get_mck_clk_rate() / 2; 99 else 100 return get_mck_clk_rate(); 101 } 102 get_twi_clk_rate(unsigned int dev_id)103static inline unsigned long get_twi_clk_rate(unsigned int dev_id) 104 { 105 if (get_h32mxdiv()) 106 return get_mck_clk_rate() / 2; 107 else 108 return get_mck_clk_rate(); 109 } 110 get_mci_clk_rate(void)111static inline unsigned long get_mci_clk_rate(void) 112 { 113 if (get_h32mxdiv()) 114 return get_mck_clk_rate() / 2; 115 else 116 return get_mck_clk_rate(); 117 } 118 get_pit_clk_rate(void)119static inline unsigned long get_pit_clk_rate(void) 120 { 121 if (get_h32mxdiv()) 122 return get_mck_clk_rate() / 2; 123 else 124 return get_mck_clk_rate(); 125 } 126 127 int at91_clock_init(unsigned long main_clock); 128 void at91_periph_clk_enable(int id); 129 void at91_periph_clk_disable(int id); 130 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div); 131 u32 at91_get_periph_generated_clk(u32 id); 132 void at91_system_clk_enable(int sys_clk); 133 void at91_system_clk_disable(int sys_clk); 134 int at91_upll_clk_enable(void); 135 int at91_upll_clk_disable(void); 136 void at91_usb_clk_init(u32 value); 137 int at91_pllb_clk_enable(u32 pllbr); 138 int at91_pllb_clk_disable(void); 139 void at91_pllicpr_init(u32 icpr); 140 141 #endif /* __ASM_ARM_ARCH_CLK_H__ */ 142