Searched refs:ginv (Results 1 – 21 of 21) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | ase_warnings.ll | 51 ; Check ginv warnings.
52 ; RUN: llc -march=mips -mattr=+mips32r2 -mattr=+ginv < %s 2>&1 | \
54 ; RUN: llc -march=mips64 -mattr=+mips64r2 -mattr=+ginv < %s 2>&1 | \
56 ; RUN: llc -march=mips -mattr=+mips32r6 -mattr=+ginv < %s 2>&1 | \
58 ; RUN: llc -march=mips64 -mattr=+mips64r6 -mattr=+ginv < %s 2>&1 | \
86 ; GINV_32: warning: the 'ginv' ASE requires MIPS32 revision 6 or greater
87 ; GINV_64: warning: the 'ginv' ASE requires MIPS64 revision 6 or greater
88 ; GINV_32_NO_WARNING-NOT: warning: the 'ginv' ASE requires MIPS32 revision 6 or greater
89 ; GINV_64_NO_WARNING-NOT: warning: the 'ginv' ASE requires MIPS64 revision 6 or greater
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ginv/ |
| D | set-ginv-directive.s | 2 # RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
4 # RUN: -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
6 .set ginv define
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| D | invalid.s | 3 # RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv 2>%t1
5 # RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+ginv 2>%t1
8 # RUN: -mattr=+micromips,+ginv 2>%t1
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| D | valid.s | 2 # RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
4 # RUN: -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
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| D | set-noginv-directive.s | 2 # RUN: -mcpu=mips32r6 -mattr=+ginv 2>%t1
5 # RUN: -mcpu=mips64r6 -mattr=+ginv 2>%t1
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| D | module-noginv.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+ginv | \
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| D | module-ginv.s | 9 # CHECK-ASM: .module ginv
17 .module ginv
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| D | valid-micromips.s | 2 # RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/ginv/ |
| D | valid-el.txt | 2 # RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
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| D | valid.txt | 2 # RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
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| D | valid-micromips-el.txt | 2 # RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
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| D | valid-micromips.txt | 2 # RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrFormats.td | 594 class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
602 let Inst{7-6} = ginv;
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| D | MicroMips32r6InstrFormats.td | 886 class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv>
897 let Inst{12-11} = ginv;
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| D | Mips.td | 185 def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 85 { "ginv", "Mips Global Invalidate ASE", { Mips::FeatureGINV }, { } },
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| /external/hyphenation-patterns/de/ |
| D | hyph-de-1901.pat.txt | 7203 2ginv
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| D | hyph-de-ch-1901.pat.txt | 7129 2ginv
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| D | hyph-de-1996.pat.txt | 7140 2ginv
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| /external/hyphenation-patterns/nb/ |
| D | hyph-nb.pat.txt | 8160 2ginv
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| /external/hyphenation-patterns/nn/ |
| D | hyph-nn.pat.txt | 8160 2ginv
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