Home
last modified time | relevance | path

Searched refs:gpu_address (Results 1 – 25 of 33) sorted by relevance

12

/external/mesa3d/src/gallium/drivers/radeon/
Dr600_buffer_common.c219 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_alloc_resource()
221 res->gpu_address = 0; in si_alloc_resource()
231 res->gpu_address, res->gpu_address + res->buf->size, in si_alloc_resource()
285 uint64_t old_gpu_address = rdst->gpu_address; in si_replace_buffer_storage()
288 rdst->gpu_address = rsrc->gpu_address; in si_replace_buffer_storage()
675 rbuffer->gpu_address = in si_buffer_from_user_memory()
678 rbuffer->gpu_address = 0; in si_buffer_from_user_memory()
Dr600_pipe_common.c80 radeon_emit(cs, scratch->gpu_address); in si_gfx_write_event_eop()
81 radeon_emit(cs, scratch->gpu_address >> 32); in si_gfx_write_event_eop()
99 uint64_t va = scratch->gpu_address; in si_gfx_write_event_eop()
Dr600_texture.c411 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
541 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_reallocate_texture_inplace()
1302 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); in r600_texture_create_object()
1340 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object()
1344 rtex->resource.gpu_address, in r600_texture_create_object()
1345 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object()
1630 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage()
2293 tex->dcc_offset = tex->dcc_separate_buffer->gpu_address; in vi_separate_dcc_try_enable()
Dr600_query.c825 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_start()
912 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_stop()
994 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset; in r600_emit_query_predication()
1004 uint64_t va_base = qbuf->buf->gpu_address; in r600_emit_query_predication()
1764 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in r600_query_hw_get_result_resource()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_buffer_common.c216 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf); in r600_alloc_resource()
218 res->gpu_address = 0; in r600_alloc_resource()
227 res->gpu_address, res->gpu_address + res->buf->size, in r600_alloc_resource()
282 uint64_t old_gpu_address = rdst->gpu_address; in r600_replace_buffer_storage()
285 rdst->gpu_address = rsrc->gpu_address; in r600_replace_buffer_storage()
664 rbuffer->gpu_address = in r600_buffer_from_user_memory()
667 rbuffer->gpu_address = 0; in r600_buffer_from_user_memory()
Devergreen_hw_context.c49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer()
50 src_offset += rsrc->gpu_address; in evergreen_dma_copy_buffer()
101 offset += r600_resource(dst)->gpu_address; in evergreen_cp_dma_clear_buffer()
Dr600_streamout.c196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address; in r600_emit_streamout_begin()
221 uint64_t va = t[i]->buf_filled_size->gpu_address + in r600_emit_streamout_begin()
267 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in r600_emit_streamout_end()
Devergreen_state.c644 va = tmp->resource.gpu_address + params->offset; in evergreen_fill_buffer_resource_words()
689 if (tmp->resource.gpu_address) in texture_buffer_sampler_view()
814 va = tmp->resource.gpu_address; in evergreen_fill_tex_resource_words()
1093 color->offset = (res->gpu_address + first_element) >> 8; in evergreen_set_color_surface_buffer()
1119 color->offset += rtex->resource.gpu_address; in evergreen_set_color_surface_common()
1264 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8; in evergreen_set_color_surface_common()
1351 offset = rtex->resource.gpu_address; in evergreen_init_depth_surface()
1403 stencil_offset += rtex->resource.gpu_address; in evergreen_init_depth_surface()
1418 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; in evergreen_init_depth_surface()
1759 …set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8); in evergreen_emit_image_state()
[all …]
Dr600_hw_context.c454 va = buf->gpu_address + offset; in r600_emit_pfp_sync_me()
504 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer()
505 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
Dr600_texture.c343 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
410 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_reallocate_texture_inplace()
716 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in r600_texture_alloc_cmask_separate()
966 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf); in r600_texture_create_object()
993 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object()
997 rtex->resource.gpu_address, in r600_texture_create_object()
998 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object()
1270 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage()
Dr600_uvd.c125 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in r600_video_buffer_create()
Dr600_query.c795 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_start()
881 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_stop()
948 uint64_t va_base = qbuf->buf->gpu_address; in r600_emit_query_predication()
1721 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in r600_query_hw_get_result_resource()
1886 radeon_emit(cs, buffer->gpu_address); in r600_query_fix_enabled_rb_mask()
1887 radeon_emit(cs, buffer->gpu_address >> 32); in r600_query_fix_enabled_rb_mask()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_dma.c250 uint64_t va = rdst->gpu_address + offset; in si_clear_buffer()
389 va = sctx->scratch_buffer->gpu_address; in si_cp_dma_realign_engine()
422 dst_offset += r600_resource(dst)->gpu_address; in si_copy_buffer()
423 src_offset += r600_resource(src)->gpu_address; in si_copy_buffer()
520 sctx->vertex_buffers.gpu_address - in cik_prefetch_VBO_descriptors()
521 sctx->vertex_buffers.buffer->gpu_address, in cik_prefetch_VBO_descriptors()
Dsi_descriptors.c158 desc->gpu_address = si_desc_extract_buffer_address(descriptor); in si_upload_descriptors()
170 desc->gpu_address = 0; in si_upload_descriptors()
183 desc->gpu_address = desc->buffer->gpu_address + buffer_offset; in si_upload_descriptors()
294 uint64_t va = buf->gpu_address + offset; in si_set_buf_desc_address()
325 va = tex->resource.gpu_address; in si_set_mutable_tex_desc_fields()
353 meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + in si_set_mutable_tex_desc_fields()
363 meta_va = tex->resource.gpu_address + tex->htile_offset; in si_set_mutable_tex_desc_fields()
979 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); in si_get_buffer_from_descriptors()
980 *offset = va - res->gpu_address; in si_get_buffer_from_descriptors()
1043 desc->gpu_address = 0; in si_upload_vertex_buffer_descriptors()
[all …]
Dsi_dma.c47 dst_offset += rdst->gpu_address; in si_dma_copy_buffer()
48 src_offset += rsrc->gpu_address; in si_dma_copy_buffer()
100 offset += rdst->gpu_address; in si_dma_clear_buffer()
186 base += rtiled->resource.gpu_address; in si_dma_copy_tile()
187 addr += rlinear->resource.gpu_address; in si_dma_copy_tile()
Dsi_compute.c269 va = r600_resource(resources[i])->gpu_address; in si_set_global_binding()
311 bc_va = sctx->border_color_buffer->gpu_address; in si_initialize_compute()
354 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in si_setup_compute_scratch_buffer()
441 shader_va = shader->bo->gpu_address + offset; in si_switch_compute_shader()
479 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in setup_scratch_rsrc_user_sgprs()
575 dispatch_va = dispatch_buf->gpu_address + dispatch_offset; in si_setup_user_sgprs_co_v2()
635 kernel_args_va = input_buffer->gpu_address + kernel_args_offset; in si_upload_compute_input()
685 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_setup_tgsi_grid()
758 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
Dcik_sdma.c46 dst_offset += rdst->gpu_address; in cik_sdma_copy_buffer()
47 src_offset += rsrc->gpu_address; in cik_sdma_copy_buffer()
91 offset += rdst->gpu_address; in cik_sdma_clear_buffer()
150 uint64_t dst_address = rdst->resource.gpu_address + in cik_sdma_copy_texture()
152 uint64_t src_address = rsrc->resource.gpu_address + in cik_sdma_copy_texture()
Dsi_pm4.c143 radeon_emit(cs, ib->gpu_address); in si_pm4_emit()
144 radeon_emit(cs, ib->gpu_address >> 32); in si_pm4_emit()
Dsi_state_streamout.c183 uint64_t va = r600_resource(buffer)->gpu_address; in si_set_streamout_targets()
283 uint64_t va = t[i]->buf_filled_size->gpu_address + in si_emit_streamout_begin()
327 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in si_emit_streamout_end()
Dsi_state_draw.c298 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16); in si_emit_derived_tess_state()
657 uint64_t va = t->buf_filled_size->gpu_address + in si_emit_draw_packets()
715 index_va = r600_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
729 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
777 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset; in si_emit_draw_packets()
1023 va = sctx->wait_mem_scratch->gpu_address; in si_emit_cache_flush()
1556 uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address; in si_trace_emit()
Dsi_uvd.c95 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in si_video_buffer_create()
Dsi_pipe.c349 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address); in si_create_context()
350 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32); in si_create_context()
602 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */ in si_test_vmfault()
Dsi_state_shaders.c455 va = shader->bo->gpu_address; in si_shader_ls()
486 va = shader->bo->gpu_address; in si_shader_hs()
540 va = shader->bo->gpu_address; in si_shader_es()
724 va = shader->bo->gpu_address; in si_shader_gs()
854 va = shader->bo->gpu_address; in si_shader_vs()
1076 va = shader->bo->gpu_address; in si_shader_ps()
2817 uint64_t scratch_va = sctx->scratch_buffer->gpu_address; in si_update_scratch_buffer()
3051 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address; in si_init_tess_factor_ring()
3052 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address; in si_init_tess_factor_ring()
Dsi_state.c2528 surf->db_depth_base = rtex->resource.gpu_address >> 8; in si_init_depth_surface()
2529 surf->db_stencil_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2569 surf->db_htile_data_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2581 surf->db_depth_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2583 surf->db_stencil_base = (rtex->resource.gpu_address + in si_init_depth_surface()
2647 surf->db_htile_data_base = (rtex->resource.gpu_address + in si_init_depth_surface()
3002 cb_color_base = tex->resource.gpu_address >> 8; in si_emit_framebuffer_state()
3009 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; in si_emit_framebuffer_state()
3023 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) + in si_emit_framebuffer_state()
3750 va = tex->resource.gpu_address + tex->fmask.offset; in si_make_texture_descriptor()
[all …]
/external/mesa3d/src/amd/vulkan/
Dradv_image.c208 uint64_t gpu_address = radv_buffer_get_va(buffer->bo); in radv_make_buffer_descriptor() local
209 uint64_t va = gpu_address + buffer->offset; in radv_make_buffer_descriptor()
245 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; in si_set_mutable_tex_desc_fields() local
246 uint64_t va = gpu_address; in si_set_mutable_tex_desc_fields()
268 meta_va = gpu_address + image->dcc_offset; in si_set_mutable_tex_desc_fields()
273 meta_va = gpu_address + image->htile_offset; in si_set_mutable_tex_desc_fields()
501 uint64_t gpu_address = radv_buffer_get_va(image->bo); in si_make_texture_descriptor() local
504 va = gpu_address + image->offset + image->fmask.offset; in si_make_texture_descriptor()

12