| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | postra-norename.mir | 4 # since V_MOV_B32_e32 has hasExtraSrcRegAllocReq set.
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 520 bool hasExtraSrcRegAllocReq() const { in hasExtraSrcRegAllocReq() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
| D | Nios2InstrInfo.td | 67 hasExtraSrcRegAllocReq = 1 in {
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 453 bool hasExtraSrcRegAllocReq() const { in hasExtraSrcRegAllocReq() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 131 FLAG(hasExtraSrcRegAllocReq) in EmitInstrDocs()
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| D | CodeGenInstruction.h | 254 bool hasExtraSrcRegAllocReq : 1; variable
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| D | InstrInfoEmitter.cpp | 599 if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq) in emitRecord()
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| D | CodeGenInstruction.cpp | 343 hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); in CodeGenInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 495 bool hasExtraSrcRegAllocReq() const { in hasExtraSrcRegAllocReq() function
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenInstruction.h | 242 bool hasExtraSrcRegAllocReq; variable
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| D | InstrInfoEmitter.cpp | 296 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 318 hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 251 bool hasExtraSrcRegAllocReq : 1; variable
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| D | InstrInfoEmitter.cpp | 504 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 338 hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 330 let hasExtraSrcRegAllocReq = 1 in {
340 } // hasExtraSrcRegAllocReq = 1
978 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
987 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1010 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1019 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 337 let hasExtraSrcRegAllocReq = 1 in {
347 } // hasExtraSrcRegAllocReq = 1
1116 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
1125 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1148 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1157 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 184 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 467 bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() || in ScanInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 167 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 197 MI->getDesc().hasExtraSrcRegAllocReq() || in PrescanInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 455 MI->getDesc().hasExtraSrcRegAllocReq() || in ScanInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 191 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 715 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 769 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
|