Searched refs:hasVGPRs (Results 1 – 12 of 12) sorted by relevance
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()319 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) { in runOnMachineFunction()344 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()361 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
94 return !hasVGPRs(RC); in isSGPRClass()112 bool hasVGPRs(const TargetRegisterClass *RC) const;
75 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); in isVGPR()77 return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg())); in isVGPR()
620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in storeRegToStackSlot()714 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in loadRegFromStackSlot()1870 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()1872 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()2238 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()2281 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()2959 if (RI.hasVGPRs(NewDstRC)) in getDestEquivalentVGPRClass()
708 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo1013 return hasVGPRs(RC); in isVGPR()
184 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) { in scanInstructions()
154 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()186 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()192 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()310 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) in phiHasVGPROperands()685 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()701 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
133 return !hasVGPRs(RC); in isSGPRClass()151 bool hasVGPRs(const TargetRegisterClass *RC) const;
920 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in storeRegToStackSlot()1021 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in loadRegFromStackSlot()2737 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()3068 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()3070 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()3511 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()3553 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()3593 if (Src.isReg() && RI.hasVGPRs(MRI.getRegClass(Src.getReg()))) in legalizeOperands()4571 if (RI.hasVGPRs(NewDstRC)) in getDestEquivalentVGPRClass()
1254 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo1508 return hasVGPRs(RC); in isVGPR()
389 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) { in scanInstructions()
1094 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass))) in legalizeScalarOperands()