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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/Hexagon/
Dtarget-flags.mir1 # RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
8 ; CHECK: target-flags(hexagon-pcrel)
9 $r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
10 ; CHECK: target-flags(hexagon-got)
11 $r0 = A2_tfrsi target-flags (hexagon-got) 0
12 ; CHECK: target-flags(hexagon-lo16)
13 $r0 = A2_tfrsi target-flags (hexagon-lo16) 0
14 ; CHECK: target-flags(hexagon-hi16)
15 $r0 = A2_tfrsi target-flags (hexagon-hi16) 0
16 ; CHECK: target-flags(hexagon-gprel)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_bit.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
10 %z = call i32 @llvm.hexagon.S2.clbp(i64 %a)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
17 %z = call i32 @llvm.hexagon.S2.cl0p(i64 %a)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
24 %z = call i32 @llvm.hexagon.S2.cl1p(i64 %a)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
31 %z = call i32 @llvm.hexagon.S4.clbpnorm(i64 %a)
[all …]
Dxtype_pred.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32)
10 %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
15 declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
17 %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
22 declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
24 %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
29 declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
31 %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
[all …]
Dxtype_alu.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare i64 @llvm.hexagon.A2.absp(i64)
11 %z = call i64 @llvm.hexagon.A2.absp(i64 %a)
17 declare i32 @llvm.hexagon.A2.abs(i32)
19 %z = call i32 @llvm.hexagon.A2.abs(i32 %a)
24 declare i32 @llvm.hexagon.A2.abssat(i32)
26 %z = call i32 @llvm.hexagon.A2.abssat(i32 %a)
32 declare i32 @llvm.hexagon.S4.addaddi(i32, i32, i32)
34 %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
[all …]
Dxtype_perm.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A2.sat(i64)
10 %z = call i32 @llvm.hexagon.A2.sat(i64 %a)
15 declare i32 @llvm.hexagon.A2.sath(i32)
17 %z = call i32 @llvm.hexagon.A2.sath(i32 %a)
22 declare i32 @llvm.hexagon.A2.satuh(i32)
24 %z = call i32 @llvm.hexagon.A2.satuh(i32 %a)
29 declare i32 @llvm.hexagon.A2.satub(i32)
31 %z = call i32 @llvm.hexagon.A2.satub(i32 %a)
[all …]
Dxtype_fp.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare float @llvm.hexagon.F2.sfadd(float, float)
11 %z = call float @llvm.hexagon.F2.sfadd(float %a, float %b)
17 declare i32 @llvm.hexagon.F2.sfclass(float, i32)
19 %z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0)
24 declare i32 @llvm.hexagon.F2.dfclass(double, i32)
26 %z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0)
32 declare i32 @llvm.hexagon.F2.sfcmpge(float, float)
34 %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b)
[all …]
Dxtype_mpy.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare i32 @llvm.hexagon.M4.mpyrr.addi(i32, i32, i32)
11 %z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b)
16 declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32)
18 %z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0)
23 declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32)
25 %z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b)
30 declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32)
32 %z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0)
[all …]
Dalu32_alu.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A2.addi(i32, i32)
10 %z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
15 declare i32 @llvm.hexagon.A2.add(i32, i32)
17 %z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
22 declare i32 @llvm.hexagon.A2.addsat(i32, i32)
24 %z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
30 declare i32 @llvm.hexagon.A2.and(i32, i32)
32 %z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
[all …]
Dxtype_complex.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i64 @llvm.hexagon.S4.vxaddsubh(i64, i64)
10 %z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b)
15 declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64)
17 %z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b)
22 declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64)
24 %z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b)
29 declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64)
31 %z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b)
[all …]
Dxtype_shift.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
15 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
17 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
[all …]
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_bit.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
10 %z = call i32 @llvm.hexagon.S2.clbp(i64 %a)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
17 %z = call i32 @llvm.hexagon.S2.cl0p(i64 %a)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
24 %z = call i32 @llvm.hexagon.S2.cl1p(i64 %a)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
31 %z = call i32 @llvm.hexagon.S4.clbpnorm(i64 %a)
[all …]
Dxtype_pred.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32)
10 %z = call i32 @llvm.hexagon.A4.cmpbgt(i32 %a, i32 %b)
15 declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32)
17 %z = call i32 @llvm.hexagon.A4.cmpbeq(i32 %a, i32 %b)
22 declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32)
24 %z = call i32 @llvm.hexagon.A4.cmpbgtu(i32 %a, i32 %b)
29 declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32)
31 %z = call i32 @llvm.hexagon.A4.cmpbgti(i32 %a, i32 0)
[all …]
Dxtype_alu.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare i64 @llvm.hexagon.A2.absp(i64)
11 %z = call i64 @llvm.hexagon.A2.absp(i64 %a)
17 declare i32 @llvm.hexagon.A2.abs(i32)
19 %z = call i32 @llvm.hexagon.A2.abs(i32 %a)
24 declare i32 @llvm.hexagon.A2.abssat(i32)
26 %z = call i32 @llvm.hexagon.A2.abssat(i32 %a)
32 declare i32 @llvm.hexagon.S4.addaddi(i32, i32, i32)
34 %z = call i32 @llvm.hexagon.S4.addaddi(i32 %a, i32 %b, i32 0)
[all …]
Dxtype_perm.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A2.sat(i64)
10 %z = call i32 @llvm.hexagon.A2.sat(i64 %a)
15 declare i32 @llvm.hexagon.A2.sath(i32)
17 %z = call i32 @llvm.hexagon.A2.sath(i32 %a)
22 declare i32 @llvm.hexagon.A2.satuh(i32)
24 %z = call i32 @llvm.hexagon.A2.satuh(i32 %a)
29 declare i32 @llvm.hexagon.A2.satub(i32)
31 %z = call i32 @llvm.hexagon.A2.satub(i32 %a)
[all …]
Dxtype_fp.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare float @llvm.hexagon.F2.sfadd(float, float)
11 %z = call float @llvm.hexagon.F2.sfadd(float %a, float %b)
17 declare i32 @llvm.hexagon.F2.sfclass(float, i32)
19 %z = call i32 @llvm.hexagon.F2.sfclass(float %a, i32 0)
24 declare i32 @llvm.hexagon.F2.dfclass(double, i32)
26 %z = call i32 @llvm.hexagon.F2.dfclass(double %a, i32 0)
32 declare i32 @llvm.hexagon.F2.sfcmpge(float, float)
34 %z = call i32 @llvm.hexagon.F2.sfcmpge(float %a, float %b)
[all …]
Dxtype_mpy.ll1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O0 < %s | \
9 declare i32 @llvm.hexagon.M4.mpyrr.addi(i32, i32, i32)
11 %z = call i32 @llvm.hexagon.M4.mpyrr.addi(i32 0, i32 %a, i32 %b)
16 declare i32 @llvm.hexagon.M4.mpyri.addi(i32, i32, i32)
18 %z = call i32 @llvm.hexagon.M4.mpyri.addi(i32 0, i32 %a, i32 0)
23 declare i32 @llvm.hexagon.M4.mpyri.addr.u2(i32, i32, i32)
25 %z = call i32 @llvm.hexagon.M4.mpyri.addr.u2(i32 %a, i32 0, i32 %b)
30 declare i32 @llvm.hexagon.M4.mpyri.addr(i32, i32, i32)
32 %z = call i32 @llvm.hexagon.M4.mpyri.addr(i32 %a, i32 %b, i32 0)
[all …]
Dalu32_alu.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i32 @llvm.hexagon.A2.addi(i32, i32)
10 %z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
15 declare i32 @llvm.hexagon.A2.add(i32, i32)
17 %z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
22 declare i32 @llvm.hexagon.A2.addsat(i32, i32)
24 %z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
30 declare i32 @llvm.hexagon.A2.and(i32, i32)
32 %z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
[all …]
Dxtype_complex.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i64 @llvm.hexagon.S4.vxaddsubh(i64, i64)
10 %z = call i64 @llvm.hexagon.S4.vxaddsubh(i64 %a, i64 %b)
15 declare i64 @llvm.hexagon.S4.vxsubaddh(i64, i64)
17 %z = call i64 @llvm.hexagon.S4.vxsubaddh(i64 %a, i64 %b)
22 declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64)
24 %z = call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %a, i64 %b)
29 declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64)
31 %z = call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %a, i64 %b)
[all …]
Dxtype_shift.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2 ; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
8 declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32)
10 %z = call i64 @llvm.hexagon.S2.asr.i.p(i64 %a, i32 0)
15 declare i64 @llvm.hexagon.S2.lsr.i.p(i64, i32)
17 %z = call i64 @llvm.hexagon.S2.lsr.i.p(i64 %a, i32 0)
22 declare i64 @llvm.hexagon.S2.asl.i.p(i64, i32)
24 %z = call i64 @llvm.hexagon.S2.asl.i.p(i64 %a, i32 0)
29 declare i32 @llvm.hexagon.S2.asr.i.r(i32, i32)
31 %z = call i32 @llvm.hexagon.S2.asr.i.r(i32 %a, i32 0)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dreg-scavengebug-4.ll1 ; RUN: llc -march=hexagon < %s
11 %v0 = tail call <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32> zeroinitializer)
21 %v4 = tail call <32 x i32> @llvm.hexagon.V6.vmpyh(<16 x i32> undef, i32 undef)
30 %v10 = tail call <16 x i32> @llvm.hexagon.V6.vlalignb(<16 x i32> %v8, <16 x i32> undef, i32 4)
31 %v11 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v8, i32 4)
32 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v10, <16 x i32> undef)
33 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v11, <16 x i32> undef)
34 …%v14 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb(<16 x i32> %v12, <16 x i32> zeroinitializer, …
35 …%v15 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v14, <16 x i32> %v12, <16 x…
36 …%v16 = tail call <16 x i32> @llvm.hexagon.V6.vlutvvb.oracc(<16 x i32> %v15, <16 x i32> %v12, <16 x…
[all …]
Dv6vect-dbl-spill.ll1 ; RUN: llc -march=hexagon -O3 < %s
9 %v0 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 16843009)
10 %v1 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> undef)
11 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffh.128B(<32 x i32> zeroinitializer)
19 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> undef, <32 x i32> undef)
20 …%v8 = tail call <1024 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v7, <32 x i32> zeroinitializer)
21 …%v9 = tail call <32 x i32> @llvm.hexagon.V6.vaddbnq.128B(<1024 x i1> %v8, <32 x i32> undef, <32 x …
22 …%v10 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> undef, i32…
23 …%v11 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> zeroinitializer, <32 x i32…
24 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffub.128B(<32 x i32> %v10, <32 x i32> undef)
[all …]
Dalu64.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
47 %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
55 %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
63 %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
71 %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
[all …]
Dreg-scavengebug.ll1 ; RUN: llc -O3 -march=hexagon < %s | FileCheck %s
4 target triple = "hexagon"
7 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
10 declare <16 x i32> @llvm.hexagon.V6.vshuffb(<16 x i32>) #0
13 declare <32 x i32> @llvm.hexagon.V6.vmpyubv(<16 x i32>, <16 x i32>) #0
16 declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0
19 declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0
31 %v7 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 32768)
32 %v8 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2147450879)
39 %v12 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v6, <16 x i32> %v11, i32 2)
[all …]
/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
47 %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
55 %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
63 %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
71 %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc1242 hexagon_A2_abs, // llvm.hexagon.A2.abs
1243 hexagon_A2_absp, // llvm.hexagon.A2.absp
1244 hexagon_A2_abssat, // llvm.hexagon.A2.abssat
1245 hexagon_A2_add, // llvm.hexagon.A2.add
1246 hexagon_A2_addh_h16_hh, // llvm.hexagon.A2.addh.h16.hh
1247 hexagon_A2_addh_h16_hl, // llvm.hexagon.A2.addh.h16.hl
1248 hexagon_A2_addh_h16_lh, // llvm.hexagon.A2.addh.h16.lh
1249 hexagon_A2_addh_h16_ll, // llvm.hexagon.A2.addh.h16.ll
1250 hexagon_A2_addh_h16_sat_hh, // llvm.hexagon.A2.addh.h16.sat.hh
1251 hexagon_A2_addh_h16_sat_hl, // llvm.hexagon.A2.addh.h16.sat.hl
[all …]

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