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Searched refs:hsub (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DCalcSpillWeights.cpp55 unsigned sub, hreg, hsub; in copyHint() local
59 hsub = mi->getOperand(1).getSubReg(); in copyHint()
63 hsub = mi->getOperand(0).getSubReg(); in copyHint()
70 return sub == hsub ? hreg : 0; in copyHint()
82 unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg); in copyHint()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DCalcSpillWeights.cpp62 unsigned sub, hreg, hsub; in copyHint() local
66 hsub = mi->getOperand(1).getSubReg(); in copyHint()
70 hsub = mi->getOperand(0).getSubReg(); in copyHint()
77 return sub == hsub ? hreg : 0; in copyHint()
/external/llvm/test/CodeGen/X86/
Dsse3-intrinsics-x86.ll37 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
40 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
45 …%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
48 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse_reload_fold.ll20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
116 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f)
132 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y)
Dsse3-intrinsics-fast-isel.ll77 %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
80 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
92 %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
95 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dstack-folding-fp-avx1.ll942 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
945 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
951 %2 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
954 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
960 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
963 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
969 %2 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
972 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/llvm/lib/CodeGen/
DCalcSpillWeights.cpp49 unsigned sub, hreg, hsub; in copyHint() local
53 hsub = mi->getOperand(1).getSubReg(); in copyHint()
57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
64 return sub == hsub ? hreg : 0; in copyHint()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dfp16-copy-gpr.mir51 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY]], %subreg.hsub
54 ; CHECK: [[SUBREG_TO_REG1:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.hsub
92 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
119 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
Dselect-insert-extract.mir101 ; CHECK: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
104 ; CHECK: [[COPY4:%[0-9]+]]:fpr16 = COPY [[COPY3]].hsub
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dhorizontal-shuffle.ll51 %1 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
52 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a2, <2 x double> %a3)
67 %1 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
68 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a2, <4 x float> %a3)
247 %1 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
248 %2 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a2, <4 x double> %a3)
263 %1 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
264 %2 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a2, <8 x float> %a3)
398 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
400 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
[all …]
Dsse_reload_fold.ll20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
116 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f)
132 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y)
Dsse3-intrinsics-fast-isel.ll81 %res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
84 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
96 %res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
99 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse3-intrinsics-x86.ll83 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
86 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
99 …%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
102 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dsse3-schedule.ll560 %1 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
562 %3 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %1, <2 x double> %2)
565 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
669 %1 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
671 %3 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %1, <4 x float> %2)
674 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
Dstack-folding-fp-avx1.ll936 %2 = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1)
939 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
945 %2 = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1)
948 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
954 %2 = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1)
957 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
963 %2 = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1)
966 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
Davx-intrinsics-x86.ll268 …%res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x dou…
271 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
279 …%res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>…
282 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dsse_reload_fold.ll20 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>)
27 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>)
81 %t = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %y, <4 x float> %f)
116 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %y, <2 x double> %f)
132 %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y)
Davx-intrinsics-x86.ll879 …%res = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double…
882 declare <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double>, <2 x double>) nounwind readnone
887 …%res = call <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> […
890 declare <4 x float> @llvm.x86.sse3.hsub.ps(<4 x float>, <4 x float>) nounwind readnone
1988 …%res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x dou…
1991 declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
1996 …%res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>…
1999 declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc817 hsub, // 7
1103 { 0, 16 }, // hsub
5133 …IndexNameTable[] = { "bsub", "dsub", "dsub0", "dsub1", "dsub2", "dsub3", "hsub", "qhisub", "qsub",…
5144 LaneBitmask(0x00000001), // hsub
5363 0xc0410020, 0xffffffff, 0xffffffff, 0x0000000f, // hsub
8762 &LaneMaskComposeSequences[0], // to hsub
8893 0, // hsub
8994 0, // hsub
9095 0, // hsub
9196 0, // hsub
[all …]
DAArch64GenDAGISel.inc77 /* 40*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
83 …st: (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64…
87 /* 66*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
93 …st: (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64…
97 /* 92*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
103 …Dst: (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64…
107 /* 116*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
113 …Dst: (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64…
148 /* 193*/ OPC_EmitInteger, MVT::i32, AArch64::hsub,
154 …st: (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.cpp79 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
81 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
DAArch64InstrInfo.td1591 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1592 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1594 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1595 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1749 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1753 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
2310 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2311 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>;
2432 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, hsub, uimm12s2, STRHui>;
2433 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, hsub, uimm12s2, STRHui>;
[all …]
DAArch64InstructionSelector.cpp335 .addUse(CopyReg, 0, AArch64::hsub); in selectFP16CopyFromGPR32()
407 .addImm(AArch64::hsub); in selectCopy()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1384 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1385 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1387 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1388 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1542 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1546 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
2092 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2093 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
3477 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3481 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
[all …]
DAArch64RegisterInfo.td26 def hsub : SubRegIndex<16>;
284 let SubRegIndices = [hsub] in {

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