Home
last modified time | relevance | path

Searched refs:hwreg (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsopk.s99 s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31)
104 s_getreg_b32 s2, hwreg(51, 1, 31)
109 s_getreg_b32 s2, hwreg(51)
114 s_getreg_b32 s2, hwreg(10)
119 s_getreg_b32 s2, hwreg(15)
140 s_setreg_b32 hwreg(HW_REG_HW_ID), s2
145 s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2
150 s_setreg_b32 hwreg(10), s2
155 s_setreg_b32 hwreg(15), s2
161 s_setreg_b32 hwreg(5, 1, 31), s2
[all …]
Dsopk-err.s9 s_setreg_b32 hwreg(0x40), s2
12 s_setreg_b32 hwreg(HW_REG_WRONG), s2
15 s_setreg_b32 hwreg(3,32,32), s2
18 s_setreg_b32 hwreg(3,0,33), s2
24 s_setreg_imm32_b32 hwreg(3,0,33), 0xff
27 s_getreg_b32 s2, hwreg(3,32,32)
30 s_getreg_b32 s2, hwreg(HW_REG_SH_MEM_BASES)
/external/llvm/test/MC/AMDGPU/
Dsopk.s82 s_getreg_b32 s2, hwreg(HW_REG_GPR_ALLOC, 1, 31)
87 s_getreg_b32 s2, hwreg(51, 1, 31)
92 s_getreg_b32 s2, hwreg(51)
112 s_setreg_b32 hwreg(HW_REG_HW_ID), s2
117 s_setreg_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), s2
122 s_setreg_b32 hwreg(5, 1, 31), s2
132 s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff
Dsopk-err.s8 s_setreg_b32 hwreg(0x40), s2
11 s_setreg_b32 hwreg(HW_REG_WRONG), s2
14 s_setreg_b32 hwreg(3,32,32), s2
17 s_setreg_b32 hwreg(3,0,33), s2
23 s_setreg_imm32_b32 hwreg(3,0,33), 0xff
26 s_getreg_b32 s2, hwreg(3,32,32)
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsopk_vi.txt51 # VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
54 # VI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
57 # VI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
60 # VI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
63 # VI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0x…
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsopk_vi.txt51 # VI: s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC) ; encoding: [0x06,0xf8,0x82,0xb8]
54 # VI: s_getreg_b32 s2, hwreg(51) ; encoding: [0x33,0xf8,0x82,0xb8]
57 # VI: s_getreg_b32 s2, hwreg(51, 1, 31) ; encoding: [0x73,0xf0,0x82,0xb8]
60 # VI: s_setreg_b32 hwreg(HW_REG_LDS_ALLOC, 0, 1), s2 ; encoding: [0x06,0x00,0x02,0xb9]
63 # VI: s_setreg_imm32_b32 hwreg(HW_REG_GPR_ALLOC, 1, 31), 0xff ; encoding: [0x45,0xf0,0x00,0xba,0x…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll6 ; GCN: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)
16 ; GCN: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)
Daddrspacecast.ll20 ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
60 ; GFX9-DAG: s_getreg_b32 [[SSRC_PRIVATE:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 0, 16)
171 ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
Dfdiv.ll20 ; GCN: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
27 ; GCN: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.getreg.ll6 ; CHECK: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23)
/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
Dradeon_compiler_regalloc_tests.c36 void (*allocate)(void * data, unsigned input, unsigned hwreg), in dummy_allocate_hw_inputs() argument
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_compiler.h124 void (*allocate)(void * data, unsigned input, unsigned hwreg),
Dradeon_pair_regalloc.c255 unsigned int hwreg) in alloc_input_simple() argument
264 s->Input[input].Index = hwreg; in alloc_input_simple()
/external/mesa3d/src/gallium/drivers/r300/
Dr300_fs.c116 void (*allocate)(void * data, unsigned input, unsigned hwreg), in allocate_hardware_inputs() argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td658 (outs SReg_32:$sdst), (ins hwreg:$simm16),
667 (outs), (ins SReg_32:$sdst, hwreg:$simm16),
677 (outs), (ins i32imm:$imm, hwreg:$simm16),
DSIInstrInfo.td775 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td405 (ins hwreg:$simm16), " $sdst, $simm16"
411 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
417 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
DSIInstrInfo.td573 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;