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Searched refs:hz (Results 1 – 25 of 386) sorted by relevance

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/external/fdlibm/
De_fmod.c35 int n,hx,hy,hz,ix,iy,sx,i; local
103 hz=hx-hy;lz=lx-ly; if(lx<ly) hz -= 1;
104 if(hz<0){hx = hx+hx+(lx>>31); lx = lx+lx;}
106 if((hz|lz)==0) /* return sign(x)*0 */
108 hx = hz+hz+(lz>>31); lx = lz+lz;
111 hz=hx-hy;lz=lx-ly; if(lx<ly) hz -= 1;
112 if(hz>=0) {hx=hz;lx=lz;}
Dk_cos.c71 double a,hz,z,r,qx; local
88 hz = 0.5*z-qx;
90 return a - (hz - (z*r-x*y));
/external/u-boot/drivers/spi/
Dcadence_qspi.c22 static int cadence_spi_write_speed(struct udevice *bus, uint hz) in cadence_spi_write_speed() argument
28 CONFIG_CQSPI_REF_CLK, hz); in cadence_spi_write_speed()
31 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
39 static int spi_calibration(struct udevice *bus, uint hz) in spi_calibration() argument
65 cadence_spi_write_speed(bus, hz); in spi_calibration()
112 priv->qspi_calibrated_hz = hz; in spi_calibration()
118 static int cadence_spi_set_speed(struct udevice *bus, uint hz) in cadence_spi_set_speed() argument
124 if (hz > plat->max_hz) in cadence_spi_set_speed()
125 hz = plat->max_hz; in cadence_spi_set_speed()
134 if (priv->previous_hz != hz || in cadence_spi_set_speed()
[all …]
/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun4i.c118 void clock_set_pll1(unsigned int hz) in clock_set_pll1() argument
126 while (pll1_para[i].freq > hz) in clock_set_pll1()
129 hz = pll1_para[i].freq; in clock_set_pll1()
130 if (! hz) in clock_set_pll1()
131 hz = 384000000; in clock_set_pll1()
134 axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */ in clock_set_pll1()
135 ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */ in clock_set_pll1()
138 printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); in clock_set_pll1()
227 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) in clock_set_de_mod_clock() argument
232 while ((pll / div) > hz) in clock_set_de_mod_clock()
/external/u-boot/lib/
Dstrmhz.c8 char *strmhz (char *buf, unsigned long hz) in strmhz() argument
13 n = DIV_ROUND_CLOSEST(hz, 1000) / 1000L; in strmhz()
16 hz -= n * 1000000L; in strmhz()
17 m = DIV_ROUND_CLOSEST(hz, 1000L); in strmhz()
/external/u-boot/arch/arm/dts/
Duniphier-pro5.dtsi43 opp-hz = /bits/ 64 <100000000>;
47 opp-hz = /bits/ 64 <116667000>;
51 opp-hz = /bits/ 64 <150000000>;
55 opp-hz = /bits/ 64 <175000000>;
59 opp-hz = /bits/ 64 <200000000>;
63 opp-hz = /bits/ 64 <233334000>;
67 opp-hz = /bits/ 64 <300000000>;
71 opp-hz = /bits/ 64 <350000000>;
75 opp-hz = /bits/ 64 <400000000>;
79 opp-hz = /bits/ 64 <466667000>;
[all …]
Dsun8i-a33.dtsi54 opp-hz = /bits/ 64 <120000000>;
60 opp-hz = /bits/ 64 <240000000>;
66 opp-hz = /bits/ 64 <312000000>;
72 opp-hz = /bits/ 64 <408000000>;
78 opp-hz = /bits/ 64 <480000000>;
84 opp-hz = /bits/ 64 <504000000>;
90 opp-hz = /bits/ 64 <600000000>;
96 opp-hz = /bits/ 64 <648000000>;
102 opp-hz = /bits/ 64 <720000000>;
108 opp-hz = /bits/ 64 <816000000>;
[all …]
Duniphier-ld20.dtsi88 opp-hz = /bits/ 64 <250000000>;
92 opp-hz = /bits/ 64 <275000000>;
96 opp-hz = /bits/ 64 <500000000>;
100 opp-hz = /bits/ 64 <550000000>;
104 opp-hz = /bits/ 64 <666667000>;
108 opp-hz = /bits/ 64 <733334000>;
112 opp-hz = /bits/ 64 <1000000000>;
116 opp-hz = /bits/ 64 <1100000000>;
126 opp-hz = /bits/ 64 <250000000>;
130 opp-hz = /bits/ 64 <275000000>;
[all …]
Duniphier-pxs3.dtsi82 opp-hz = /bits/ 64 <250000000>;
86 opp-hz = /bits/ 64 <325000000>;
90 opp-hz = /bits/ 64 <500000000>;
94 opp-hz = /bits/ 64 <650000000>;
98 opp-hz = /bits/ 64 <666667000>;
102 opp-hz = /bits/ 64 <866667000>;
106 opp-hz = /bits/ 64 <1000000000>;
110 opp-hz = /bits/ 64 <1300000000>;
Duniphier-pxs2.dtsi67 opp-hz = /bits/ 64 <100000000>;
71 opp-hz = /bits/ 64 <150000000>;
75 opp-hz = /bits/ 64 <200000000>;
79 opp-hz = /bits/ 64 <300000000>;
83 opp-hz = /bits/ 64 <400000000>;
87 opp-hz = /bits/ 64 <600000000>;
91 opp-hz = /bits/ 64 <800000000>;
95 opp-hz = /bits/ 64 <1200000000>;
Duniphier-ld11.dtsi58 opp-hz = /bits/ 64 <245000000>;
62 opp-hz = /bits/ 64 <250000000>;
66 opp-hz = /bits/ 64 <490000000>;
70 opp-hz = /bits/ 64 <500000000>;
74 opp-hz = /bits/ 64 <653334000>;
78 opp-hz = /bits/ 64 <666667000>;
82 opp-hz = /bits/ 64 <980000000>;
/external/python/cpython2/Modules/cjkcodecs/
D_codecs_cn.c15 #undef hz
315 ENCODER_INIT(hz) in ENCODER_INIT() argument
321 ENCODER_RESET(hz) in ENCODER_RESET() argument
331 ENCODER(hz) in ENCODER() argument
374 DECODER_INIT(hz) in DECODER_INIT() argument
380 DECODER_RESET(hz) in DECODER_RESET() argument
386 DECODER(hz) in DECODER() argument
444 CODEC_STATEFUL(hz)
/external/python/cpython3/Modules/cjkcodecs/
D_codecs_cn.c15 #undef hz
330 ENCODER_INIT(hz) in ENCODER_INIT() argument
336 ENCODER_RESET(hz) in ENCODER_RESET() argument
346 ENCODER(hz) in ENCODER() argument
392 DECODER_INIT(hz) in DECODER_INIT() argument
398 DECODER_RESET(hz) in DECODER_RESET() argument
404 DECODER(hz) in DECODER() argument
461 CODEC_STATEFUL(hz)
/external/deqp/framework/opengl/simplereference/
DsglrContextUtil.cpp47 float hz = (p0.z() + p1.z()) * 0.5f; in drawQuadWithVaoBuffers() local
51 p0.x(), p1.y(), hz, 1.0f, in drawQuadWithVaoBuffers()
52 p1.x(), p0.y(), hz, 1.0f, in drawQuadWithVaoBuffers()
117 float hz = (p0.z() + p1.z()) * 0.5f; in drawQuadWithClientPointers() local
121 p0.x(), p1.y(), hz, 1.0f, in drawQuadWithClientPointers()
122 p1.x(), p0.y(), hz, 1.0f, in drawQuadWithClientPointers()
/external/u-boot/drivers/clk/rockchip/
Dclk_rv1108.c29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
33 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
34 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
35 #hz "Hz cannot be hit with PLL "\
143 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk() argument
147 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
Dclk_rk3128.c29 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
31 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
367 static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_peri_set_pclk() argument
371 src_clk_div = PERI_ACLK_HZ / hz; in rk3128_peri_set_pclk()
402 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) in rk3128_saradc_set_clk() argument
406 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
416 static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) in rk3128_vop_set_clk() argument
421 src_clk_div = GPLL_HZ / hz; in rk3128_vop_set_clk()
438 if (pll_para_config(hz, &cpll_config)) in rk3128_vop_set_clk()
452 return hz; in rk3128_vop_set_clk()
Dclk_rk3188.c73 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
74 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
75 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
76 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
120 unsigned int hz, bool has_bwadj) in rkclk_configure_ddr() argument
130 switch (hz) { in rkclk_configure_ddr()
166 unsigned int hz, bool has_bwadj) in rkclk_configure_cpu() argument
181 switch (hz) { in rkclk_configure_cpu()
221 return hz; in rkclk_configure_cpu()
Dclk_rk3368.c43 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
44 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
45 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
46 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
400 static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz) in rk3368_spi_set_clk() argument
405 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); in rk3368_spi_set_clk()
438 static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz) in rk3368_saradc_set_clk() argument
442 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3368_saradc_set_clk()
Dclk_rk3399.c44 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
492 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_i2c_set_clk() argument
497 src_clk_div = GPLL_HZ / hz; in rk3399_i2c_set_clk()
591 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) in rk3399_spi_set_clk() argument
596 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rk3399_spi_set_clk()
618 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) in rk3399_vop_set_clk() argument
647 if (pll_para_config(hz, &vpll_config)) in rk3399_vop_set_clk()
659 return hz; in rk3399_vop_set_clk()
816 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) in rk3399_saradc_set_clk() argument
[all …]
Dclk_rk3328.c32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
358 static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) in rk3328_i2c_set_clk() argument
362 src_clk_div = GPLL_HZ / hz; in rk3328_i2c_set_clk()
515 static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_pwm_set_clk() argument
517 u32 div = GPLL_HZ / hz; in rk3328_pwm_set_clk()
538 static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) in rk3328_saradc_set_clk() argument
542 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
Dclk_rk3036.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
37 #hz "Hz cannot be hit with PLL "\
Dclk_rk3288.c132 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
133 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
134 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
135 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
175 unsigned int hz) in rkclk_configure_ddr() argument
185 switch (hz) { in rkclk_configure_ddr()
684 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz) in rockchip_saradc_set_clk() argument
688 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rockchip_saradc_set_clk()
/external/u-boot/drivers/mmc/
Dsunxi_mmc.c96 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) in mmc_set_mod_clk() argument
110 hz = hz * 2; in mmc_set_mod_clk()
112 if (hz <= 24000000) { in mmc_set_mod_clk()
125 div = pll_hz / hz; in mmc_set_mod_clk()
126 if (pll_hz % hz) in mmc_set_mod_clk()
137 hz); in mmc_set_mod_clk()
142 if (hz <= 400000) { in mmc_set_mod_clk()
145 } else if (hz <= 25000000) { in mmc_set_mod_clk()
149 } else if (hz <= 52000000) { in mmc_set_mod_clk()
157 } else if (hz <= 52000000) { in mmc_set_mod_clk()
[all …]
/external/ltp/testcases/kernel/syscalls/adjtimex/
Dadjtimex02.c110 static int hz; /* HZ from sysconf */ variable
209 hz = SAFE_SYSCONF(NULL, _SC_CLK_TCK); in setup()
235 buff.tick = 900000 / hz - 1; in setup2()
241 buff.tick = 1100000 / hz + 1; in setup3()
/external/u-boot/drivers/clk/
Dclk_pic32.c117 ulong hz; in pic32_get_sysclk() local
129 hz = SYS_FRC_CLK_HZ / div; in pic32_get_sysclk()
133 hz = pic32_get_pll_rate(priv); in pic32_get_sysclk()
137 hz = SYS_POSC_CLK_HZ; in pic32_get_sysclk()
141 hz = 0; in pic32_get_sysclk()
146 return hz; in pic32_get_sysclk()

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