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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/
DBranchSelector.ll5 @reg = common global i16 0, align 2
7 define void @WriteBurstPATable(i16 %count) #0 {
12 store volatile i16 11, i16* @reg, align 2
13 store volatile i16 13, i16* @reg, align 2
14 store volatile i16 17, i16* @reg, align 2
15 store volatile i16 11, i16* @reg, align 2
16 store volatile i16 13, i16* @reg, align 2
17 store volatile i16 17, i16* @reg, align 2
18 store volatile i16 11, i16* @reg, align 2
19 store volatile i16 13, i16* @reg, align 2
[all …]
Dmult-alt-generic-msp430.ll3 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
6 @mout0 = common global i16 0, align 2
7 @min1 = common global i16 0, align 2
8 @marray = common global [2 x i16] zeroinitializer, align 2
12 call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind
18 %out0 = alloca i16, align 2
19 %index = alloca i16, align 2
20 store i16 0, i16* %out0, align 2
21 store i16 1, i16* %index, align 2
32 %out0 = alloca i16, align 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/vect/
Dvect-bad-bitcast.ll8 …i16] [i16 0, i16 0, i16 0, i16 1280, i16 2560, i16 4864, i16 7168, i16 9472, i16 11776, i16 12672,…
13 %WaterLeveldB_out = alloca i16, align 2
18 …@fxpBitAllocation to i32 (i32, i32, i32, i32, i16*, i32, i32, i32)*)(i32 0, i32 0, i32 256, i32 %c…
27 %WaterLeveldB.1p_vsel.lcssa = phi <4 x i16> [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ]
28 …%_low_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 …
29 …%_high_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32…
30 %0 = icmp sgt <2 x i16> %_low_half, %_high_half
31 %1 = select <2 x i1> %0, <2 x i16> %_low_half, <2 x i16> %_high_half
32 %2 = extractelement <2 x i16> %1, i32 0
33 %3 = extractelement <2 x i16> %1, i32 1
[all …]
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-bad-bitcast.ll8 …i16] [i16 0, i16 0, i16 0, i16 1280, i16 2560, i16 4864, i16 7168, i16 9472, i16 11776, i16 12672,…
13 %WaterLeveldB_out = alloca i16, align 2
18 …@fxpBitAllocation to i32 (i32, i32, i32, i32, i16*, i32, i32, i32)*)(i32 0, i32 0, i32 256, i32 %c…
27 %WaterLeveldB.1p_vsel.lcssa = phi <4 x i16> [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ]
28 …%_low_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 …
29 …%_high_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32…
30 %0 = icmp sgt <2 x i16> %_low_half, %_high_half
31 %1 = select <2 x i1> %0, <2 x i16> %_low_half, <2 x i16> %_high_half
32 %2 = extractelement <2 x i16> %1, i32 0
33 %3 = extractelement <2 x i16> %1, i32 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvector-shuffle-combining-avx512bwvl.ll5 declare <16 x i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
6 declare <16 x i16> @llvm.x86.avx512.mask.vpermi2var.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)
8 define <16 x i16> @combine_vpermt2var_16i16_identity(<16 x i16> %x0, <16 x i16> %x1) {
16 …i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, …
17 …i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, …
18 ret <16 x i16> %res1
20 define <16 x i16> @combine_vpermt2var_16i16_identity_mask(<16 x i16> %x0, <16 x i16> %x1, i16 %m) {
38 …i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, …
39 …i16> @llvm.x86.avx512.maskz.vpermt2var.hi.256(<16 x i16> <i16 15, i16 30, i16 13, i16 28, i16 11, …
40 ret <16 x i16> %res1
[all …]
Davg-mask.ll5 define <16 x i8> @avg_v16i8_mask(<16 x i8> %a, <16 x i8> %b, <16 x i8> %src, i16 %mask) nounwind {
22 %za = zext <16 x i8> %a to <16 x i16>
23 %zb = zext <16 x i8> %b to <16 x i16>
24 %add = add nuw nsw <16 x i16> %za, %zb
25 …d nuw nsw <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, …
26 …hr = lshr <16 x i16> %add1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1,…
27 %trunc = trunc <16 x i16> %lshr to <16 x i8>
28 %mask1 = bitcast i16 %mask to <16 x i1>
33 define <16 x i8> @avg_v16i8_maskz(<16 x i8> %a, <16 x i8> %b, i16 %mask) nounwind {
49 %za = zext <16 x i8> %a to <16 x i16>
[all …]
Dpic-load-remat.ll8 …3 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
9 …3 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
10 …<8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, …
11 …%tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <…
12 …ll <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x i32> < i32 4, i32 …
13 …i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
15 %tmp4689 = add <8 x i16> %tmp4679, %tmp4658 ; <<8 x i16>> [#uses=1]
16 …4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializer )…
17 %tmp4708 = bitcast <8 x i16> %tmp4700 to <2 x i64> ; <<2 x i64>> [#uses=1]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dicmp16.ll13 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-…
28 ; i16 integer comparisons:
29 define i16 @icmp_eq_select_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
31 %A = icmp eq i16 %arg1, %arg2
32 %B = select i1 %A, i16 %val1, i16 %val2
33 ret i16 %B
36 define i1 @icmp_eq_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwind {
38 %A = icmp eq i16 %arg1, %arg2
42 define i16 @icmp_eq_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
44 %A = icmp eq i16 %arg1, 511
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-const-08.ll6 define <8 x i16> @f1() {
10 ret <8 x i16> <i16 257, i16 257, i16 257, i16 257,
11 i16 257, i16 257, i16 257, i16 257>
15 define <8 x i16> @f2() {
19 ret <8 x i16> <i16 51657, i16 51657, i16 51657, i16 51657,
20 i16 51657, i16 51657, i16 51657, i16 51657>
24 define <8 x i16> @f3() {
28 ret <8 x i16> <i16 -258, i16 -258, i16 -258, i16 -258,
29 i16 -258, i16 -258, i16 -258, i16 -258>
33 define <8 x i16> @f4() {
[all …]
Dvec-const-14.ll7 define <8 x i16> @f1() {
11 ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768,
12 i16 0, i16 32768, i16 0, i16 32768>
16 define <8 x i16> @f2() {
20 ret <8 x i16> <i16 1, i16 -1, i16 1, i16 -1,
21 i16 1, i16 -1, i16 1, i16 -1>
25 define <8 x i16> @f3() {
29 ret <8 x i16> <i16 -2, i16 0, i16 -2, i16 0,
30 i16 -2, i16 0, i16 -2, i16 0>
34 define <8 x i16> @f4() {
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-const-08.ll6 define <8 x i16> @f1() {
10 ret <8 x i16> <i16 257, i16 257, i16 257, i16 257,
11 i16 257, i16 257, i16 257, i16 257>
15 define <8 x i16> @f2() {
19 ret <8 x i16> <i16 51657, i16 51657, i16 51657, i16 51657,
20 i16 51657, i16 51657, i16 51657, i16 51657>
24 define <8 x i16> @f3() {
28 ret <8 x i16> <i16 -258, i16 -258, i16 -258, i16 -258,
29 i16 -258, i16 -258, i16 -258, i16 -258>
33 define <8 x i16> @f4() {
[all …]
Dvec-const-14.ll7 define <8 x i16> @f1() {
11 ret <8 x i16> <i16 0, i16 32768, i16 0, i16 32768,
12 i16 0, i16 32768, i16 0, i16 32768>
16 define <8 x i16> @f2() {
20 ret <8 x i16> <i16 1, i16 -1, i16 1, i16 -1,
21 i16 1, i16 -1, i16 1, i16 -1>
25 define <8 x i16> @f3() {
29 ret <8 x i16> <i16 -2, i16 0, i16 -2, i16 0,
30 i16 -2, i16 0, i16 -2, i16 0>
34 define <8 x i16> @f4() {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dopt-glob-addrs-003.ll7 …{ i16, i16, [4 x i16], i16, i16, [3 x i16], [3 x [4 x i16]], [3 x i16], [2 x [2 x i16]], i16, i16,…
9 @g0 = external global i16
10 @g1 = external global [2 x i16]
11 @g2 = external global [10 x i16]
13 @g4 = external global [160 x i16]
14 @g5 = external global i16
15 @g6 = external global i16
16 @g7 = external global i16
17 @g8 = external global i16
18 @g9 = external global i16
[all …]
Disel-simplify-crash.ll7 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64…
10 define void @fred(i16 signext %a0, <32 x i16>* %a1, <32 x i16> %a3) #0 {
12 %v4 = add i16 undef, %a0
16 %v6 = insertelement <32 x i16> undef, i16 %v4, i32 0
17 %v7 = shufflevector <32 x i16> %v6, <32 x i16> undef, <32 x i32> zeroinitializer
18 …i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12…
19 %v9 = mul <32 x i16> %v8, %a3
20 %v10 = add <32 x i16> %v7, %v9
21 store <32 x i16> %v10, <32 x i16>* %a1, align 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Scalarizer/
Dvector-gep.ll5 @vec = global <4 x i16*> <i16* null, i16* null, i16* null, i16* null>
6 @index = global i16 1
7 @ptr = global [4 x i16] [i16 1, i16 2, i16 3, i16 4]
8 @ptrptr = global i16* null
13 %0 = load <4 x i16*>, <4 x i16*>* @vec
14 %1 = getelementptr i16, <4 x i16*> %0, i16 1
20 ;CHECK: %[[I0:.i[0-9]*]] = extractelement <4 x i16*> %0, i32 0
21 ;CHECK: getelementptr i16, i16* %[[I0]], i16 1
22 ;CHECK: %[[I1:.i[0-9]*]] = extractelement <4 x i16*> %0, i32 1
23 ;CHECK: getelementptr i16, i16* %[[I1]], i16 1
[all …]
/external/llvm/test/CodeGen/MSP430/
Dmult-alt-generic-msp430.ll3 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
6 @mout0 = common global i16 0, align 2
7 @min1 = common global i16 0, align 2
8 @marray = common global [2 x i16] zeroinitializer, align 2
12 call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind
18 %out0 = alloca i16, align 2
19 %index = alloca i16, align 2
20 store i16 0, i16* %out0, align 2
21 store i16 1, i16* %index, align 2
32 %out0 = alloca i16, align 2
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/MSP430/
Dmult-alt-generic-msp430.ll3 target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
6 @mout0 = common global i16 0, align 2
7 @min1 = common global i16 0, align 2
8 @marray = common global [2 x i16] zeroinitializer, align 2
12 call void asm "foo $1,$0", "=*m,*m"(i16* @mout0, i16* @min1) nounwind
18 %out0 = alloca i16, align 2
19 %index = alloca i16, align 2
20 store i16 0, i16* %out0, align 2
21 store i16 1, i16* %index, align 2
32 %out0 = alloca i16, align 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AArch64/
DPR38339.ll4 define void @f1(<2 x i16> %x, i16* %a) {
6 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i16> [[X:%.*]], <2 x i16> undef, <4 x i32> <i…
7 ; CHECK-NEXT: [[PTR0:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 0
8 ; CHECK-NEXT: [[PTR1:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 1
9 ; CHECK-NEXT: [[PTR2:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 2
10 ; CHECK-NEXT: [[PTR3:%.*]] = getelementptr inbounds [4 x i16], [4 x i16]* undef, i16 0, i16 3
11 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i16> [[SHUFFLE]], i32 0
12 ; CHECK-NEXT: store i16 [[TMP1]], i16* [[A:%.*]]
13 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[PTR0]] to <4 x i16>*
14 ; CHECK-NEXT: store <4 x i16> [[SHUFFLE]], <4 x i16>* [[TMP2]], align 2
[all …]
/external/llvm/test/CodeGen/Mips/msa/
D3rf_4rf_q.ll7 @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7…
8 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, …
9 @llvm_mips_madd_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22…
10 @llvm_mips_madd_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0…
14 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG1
15 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG2
16 %2 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG3
17 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
18 store <8 x i16> %3, <8 x i16>* @llvm_mips_madd_q_h_RES
22 declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
D3rf_4rf_q.ll7 @llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7…
8 @llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, …
9 @llvm_mips_madd_q_h_ARG3 = global <8 x i16> <i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22…
10 @llvm_mips_madd_q_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0…
14 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG1
15 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG2
16 %2 = load <8 x i16>, <8 x i16>* @llvm_mips_madd_q_h_ARG3
17 %3 = tail call <8 x i16> @llvm.mips.madd.q.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
18 store <8 x i16> %3, <8 x i16>* @llvm_mips_madd_q_h_RES
22 declare <8 x i16> @llvm.mips.madd.q.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dx86-vector-shifts.ll9 define <8 x i16> @sse2_psrai_w_0(<8 x i16> %v) {
11 ; CHECK-NEXT: ret <8 x i16> %v
13 %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 0)
14 ret <8 x i16> %1
17 define <8 x i16> @sse2_psrai_w_15(<8 x i16> %v) {
19 ; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> %v, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15,…
20 ; CHECK-NEXT: ret <8 x i16> [[TMP1]]
22 %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 15)
23 ret <8 x i16> %1
26 define <8 x i16> @sse2_psrai_w_64(<8 x i16> %v) {
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dbyval4.ll27 %struct.s = type { i16, i16, i16, i16, i16, i16, i16, i16,
28 i16, i16, i16, i16, i16, i16, i16, i16,
29 i16, i16, i16, i16, i16, i16, i16, i16,
30 i16, i16, i16, i16, i16, i16, i16, i16,
31 i16, i16, i16, i16, i16, i16, i16, i16,
32 i16, i16, i16, i16, i16, i16, i16, i16,
33 i16, i16, i16, i16, i16, i16, i16, i16,
34 i16, i16, i16, i16, i16, i16, i16, i16,
35 i16 }
38 define void @g(i16 signext %a1, i16 signext %a2, i16 signext %a3,
[all …]
Dpic-load-remat.ll8 …3 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
9 …3 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
10 …<8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, …
11 …%tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <…
12 …ll <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x i32> < i32 4, i32 …
13 …i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
15 %tmp4689 = add <8 x i16> %tmp4679, %tmp4658 ; <<8 x i16>> [#uses=1]
16 …4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializer )…
17 %tmp4708 = bitcast <8 x i16> %tmp4700 to <2 x i64> ; <<2 x i64>> [#uses=1]
[all …]
/external/llvm/test/CodeGen/X86/
Dpic-load-remat.ll8 …3 = tail call <8 x i16> @llvm.x86.sse2.psubs.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
9 …3 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> zeroinitializer, <8 x i16> zeroinitializ…
10 …<8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, …
11 …%tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <…
12 …ll <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp4651, <8 x i16> bitcast (<4 x i32> < i32 4, i32 …
13 …i16> @llvm.x86.sse2.pavg.w( <8 x i16> < i16 -23170, i16 -23170, i16 -23170, i16 -23170, i16 -23170…
14 …%tmp4679 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4669, <8 x i16> %tmp4669 ) no…
15 %tmp4689 = add <8 x i16> %tmp4679, %tmp4658 ; <<8 x i16>> [#uses=1]
16 …4700 = tail call <8 x i16> @llvm.x86.sse2.padds.w( <8 x i16> %tmp4689, <8 x i16> zeroinitializer )…
17 %tmp4708 = bitcast <8 x i16> %tmp4700 to <2 x i64> ; <<2 x i64>> [#uses=1]
[all …]
/external/llvm/test/Transforms/BBVectorize/
Dvector-sel.ll5 @d = external global [1 x [10 x [1 x i16]]], align 16
8 ;CHECK: %0 = select i1 %bool, <4 x i16> <i16 -2, i16 -2, i16 -2, i16 -2>, <4 x i16> <i16 -3, i16 -3…
9 ;CHECK: %1 = select i1 %bool, <4 x i16> <i16 -2, i16 -2, i16 -2, i16 -2>, <4 x i16> <i16 -3, i16 -3…
10 ;CHECK: %2 = shufflevector <4 x i16> %0, <4 x i16> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4…
12 …CHECK: %4 = select <8 x i1> %3, <8 x i16> <i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3, i16 -3,…
20 …%0 = select i1 %bool, <4 x i16> <i16 -2, i16 -2, i16 -2, i16 -2>, <4 x i16> <i16 -3, i16 -3, i16 -…
21 …%1 = select i1 %bool, <4 x i16> <i16 -2, i16 -2, i16 -2, i16 -2>, <4 x i16> <i16 -3, i16 -3, i16 -…
22 %2 = select <4 x i1> %boolvec, <4 x i16> <i16 -3, i16 -3, i16 -3, i16 -3>, <4 x i16> %0
23 %3 = select <4 x i1> %boolvec, <4 x i16> <i16 -3, i16 -3, i16 -3, i16 -3>, <4 x i16> %1
24 %4 = add nsw <4 x i16> %2, zeroinitializer
[all …]

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