/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
D | should-change-type.ll | 44 define i9 @test4(i9 %x, i9 %y) { 46 ; CHECK-NEXT: [[XZ:%.*]] = zext i9 [[X:%.*]] to i64 47 ; CHECK-NEXT: [[YZ:%.*]] = zext i9 [[Y:%.*]] to i64 49 ; CHECK-NEXT: [[D:%.*]] = trunc i64 [[C]] to i9 50 ; CHECK-NEXT: ret i9 [[D]] 52 %xz = zext i9 %x to i64 53 %yz = zext i9 %y to i64 55 %d = trunc i64 %c to i9 56 ret i9 %d
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D | udivrem-change-width.ll | 95 define i32 @udiv_illegal_type(i9 %a, i9 %b) { 97 ; CHECK-NEXT: [[DIV:%.*]] = udiv i9 %a, %b 98 ; CHECK-NEXT: [[UDIV:%.*]] = zext i9 [[DIV]] to i32 101 %za = zext i9 %a to i32 102 %zb = zext i9 %b to i32 148 define i32 @urem_illegal_type(i9 %a, i9 %b) { 150 ; CHECK-NEXT: [[TMP1:%.*]] = urem i9 %a, %b 151 ; CHECK-NEXT: [[UREM:%.*]] = zext i9 [[TMP1]] to i32 154 %za = zext i9 %a to i32 155 %zb = zext i9 %b to i32 [all …]
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D | apint-shift.ll | 93 define i9 @multiuse_lshr_lshr(i9 %x) { 95 ; CHECK-NEXT: [[SH1:%.*]] = lshr i9 %x, 2 96 ; CHECK-NEXT: [[SH2:%.*]] = lshr i9 %x, 5 97 ; CHECK-NEXT: [[MUL:%.*]] = mul i9 [[SH1]], [[SH2]] 98 ; CHECK-NEXT: ret i9 [[MUL]] 100 %sh1 = lshr i9 %x, 2 101 %sh2 = lshr i9 %sh1, 3 102 %mul = mul i9 %sh1, %sh2 103 ret i9 %mul 106 define <2 x i9> @multiuse_lshr_lshr_splat(<2 x i9> %x) { [all …]
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D | icmp-bc-vec.ll | 117 define i1 @extending_shuffle_with_weird_types(<2 x i9> %v) { 119 ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i9> [[V:%.*]], i32 0 120 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i9 [[TMP1]], 1 123 %splat = shufflevector <2 x i9> %v, <2 x i9> undef, <3 x i32> zeroinitializer 124 %cast = bitcast <3 x i9> %splat to i27
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/ |
D | weird-type-accesses.ll | 14 declare void @use_v2i9(<2 x i9>) 178 ; CHECK: store i9 3 179 ; CHECK: store i9 -5 180 define amdgpu_kernel void @merge_store_2_constants_i9(i9 addrspace(1)* %out) #0 { 181 %out.gep.1 = getelementptr i9, i9 addrspace(1)* %out, i32 1 182 store i9 3, i9 addrspace(1)* %out.gep.1 183 store i9 -5, i9 addrspace(1)* %out 188 ; CHECK: load <2 x i9> 189 ; CHECK: load <2 x i9> 190 define amdgpu_kernel void @merge_load_2_constants_v2i9(<2 x i9> addrspace(1)* %out) #0 { [all …]
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/external/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/ |
D | weird-type-accesses.ll | 14 declare void @use_v2i9(<2 x i9>) 178 ; CHECK: store i9 3 179 ; CHECK: store i9 -5 180 define void @merge_store_2_constants_i9(i9 addrspace(1)* %out) #0 { 181 %out.gep.1 = getelementptr i9, i9 addrspace(1)* %out, i32 1 182 store i9 3, i9 addrspace(1)* %out.gep.1 183 store i9 -5, i9 addrspace(1)* %out 188 ; CHECK: load <2 x i9> 189 ; CHECK: load <2 x i9> 190 define void @merge_load_2_constants_v2i9(<2 x i9> addrspace(1)* %out) #0 { [all …]
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/external/llvm/test/Transforms/InstSimplify/ |
D | shift-knownbits.ll | 59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) { 61 ; CHECK-NEXT: ret i9 %a 63 %and = and i9 %b, 496 ; 0x1f0 64 %shl = shl i9 %a, %and 65 ret i9 %shl 71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) { 73 ; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8 74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]] 75 ; CHECK-NEXT: ret i9 [[SHL]] 77 %and = and i9 %b, 504 ; 0x1f8 [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/ |
D | shift-knownbits.ll | 59 define i9 @shl_amount_is_zero(i9 %a, i9 %b) { 61 ; CHECK-NEXT: ret i9 %a 63 %and = and i9 %b, 496 ; 0x1f0 64 %shl = shl i9 %a, %and 65 ret i9 %shl 71 define i9 @shl_amount_is_not_known_zero(i9 %a, i9 %b) { 73 ; CHECK-NEXT: [[AND:%.*]] = and i9 %b, -8 74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]] 75 ; CHECK-NEXT: ret i9 [[SHL]] 77 %and = and i9 %b, 504 ; 0x1f8 [all …]
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D | call.ll | 451 declare i9 @llvm.fshr.i9(i9, i9, i9) 463 define i9 @fshr_no_shift(i9 %x, i9 %y) { 465 ; CHECK-NEXT: ret i9 [[Y:%.*]] 467 %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 0) 468 ret i9 %z 479 define i9 @fshr_no_shift_modulo_bitwidth(i9 %x, i9 %y) { 481 ; CHECK-NEXT: ret i9 [[Y:%.*]] 483 %z = call i9 @llvm.fshr.i9(i9 %x, i9 %y, i9 189) 484 ret i9 %z
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/external/swiftshader/third_party/LLVM/test/Analysis/ScalarEvolution/ |
D | sext-iv-1.ll | 17 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 18 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 40 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 41 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 63 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 64 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 86 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 87 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
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/external/llvm/test/Analysis/ScalarEvolution/ |
D | sext-iv-1.ll | 24 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 47 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 70 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 71 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 93 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 94 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/ |
D | sext-iv-1.ll | 24 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 25 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 47 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 48 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 70 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 71 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] 93 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] 94 %2 = sext i9 %1 to i64 ; <i64> [#uses=1]
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/external/clang/test/CodeGen/ |
D | arm64-arguments.c | 298 int i9, s38_no_align s1, s38_no_align s2) { in f38_stack() argument 308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack() 351 int i9, s39_with_align s1, s39_with_align s2) { in f39_stack() argument 361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack() 406 int i9, s40_no_align s1, s40_no_align s2) { in f40_stack() argument 416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack() 461 int i9, s41_with_align s1, s41_with_align s2) { in f41_stack() argument 471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack() 518 int i9, s42_no_align s1, s42_no_align s2) { in f42_stack() argument 524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack() [all …]
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | 2009-07-20-DAGCombineBug.ll | 14 bb3.i9: ; preds = %bb3.i17 17 bb1.i15: ; preds = %bb3.i9 20 bb2.i16: ; preds = %bb3.i9 24 br i1 false, label %bb3.i9, label %bsR.exit18
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
D | 2009-07-20-DAGCombineBug.ll | 14 bb3.i9: ; preds = %bb3.i17 17 bb1.i15: ; preds = %bb3.i9 20 bb2.i16: ; preds = %bb3.i9 24 br i1 false, label %bb3.i9, label %bsR.exit18
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/external/llvm/test/CodeGen/X86/ |
D | 2009-07-20-DAGCombineBug.ll | 14 bb3.i9: ; preds = %bb3.i17 17 bb1.i15: ; preds = %bb3.i9 20 bb2.i16: ; preds = %bb3.i9 24 br i1 false, label %bb3.i9, label %bsR.exit18
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/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-nm/X86/ |
D | radix.s | 74 .type i9,@object # @i9 75 .globl i9 symbol 77 i9: label 79 .size i9, 4
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/external/llvm/test/tools/llvm-nm/X86/ |
D | radix.s | 74 .type i9,@object # @i9 75 .globl i9 symbol 77 i9: label 79 .size i9, 4
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/external/llvm/test/CodeGen/ARM/ |
D | 2009-06-02-ISelCrash.ll | 38 bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer 42 br i1 undef, label %bb2.i9.i, label %bb1.i.i 44 bb2.i9.i: ; preds = %bb1.i.i 47 bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | 2009-06-02-ISelCrash.ll | 38 bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer 42 br i1 undef, label %bb2.i9.i, label %bb1.i.i 44 bb2.i9.i: ; preds = %bb1.i.i 47 bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | 2009-06-02-ISelCrash.ll | 38 bb1.outer2.i.i: ; preds = %bb2.i9.i, %bb1.outer2.i.i.outer 42 br i1 undef, label %bb2.i9.i, label %bb1.i.i 44 bb2.i9.i: ; preds = %bb1.i.i 47 bb4.i11.i: ; preds = %bb4.i11.i, %bb2.i9.i
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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
D | apint-sub.ll | 73 define i1 @test11(i9 %A, i9 %B) { 74 %C = sub i9 %A, %B ; <i9> [#uses=1] 75 %cD = icmp ne i9 %C, 0 ; <i1> [#uses=1]
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/external/llvm/test/Transforms/InstCombine/ |
D | apint-sub.ll | 73 define i1 @test11(i9 %A, i9 %B) { 74 %C = sub i9 %A, %B ; <i9> [#uses=1] 75 %cD = icmp ne i9 %C, 0 ; <i1> [#uses=1]
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/external/llvm/test/CodeGen/AMDGPU/ |
D | si-vector-hang.ll | 31 %arrayidx2.i9.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 5 32 %10 = load i8, i8 addrspace(1)* %arrayidx2.i9.i, align 1 55 %arrayidx2.i9.i8 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 5 56 %26 = load i8, i8 addrspace(1)* %arrayidx2.i9.i8, align 1 58 %arrayidx6.i11.i9 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 6 59 %28 = load i8, i8 addrspace(1)* %arrayidx6.i11.i9, align 1
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | si-vector-hang.ll | 31 %arrayidx2.i9.i = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 5 32 %10 = load i8, i8 addrspace(1)* %arrayidx2.i9.i, align 1 55 %arrayidx2.i9.i8 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 5 56 %26 = load i8, i8 addrspace(1)* %arrayidx2.i9.i8, align 1 58 %arrayidx6.i11.i9 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 6 59 %28 = load i8, i8 addrspace(1)* %arrayidx6.i11.i9, align 1
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