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Searched refs:if_id (Results 1 – 19 of 19) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_pbs.c45 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
56 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_pbs()
60 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
65 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs()
85 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_pbs()
86 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_pbs()
87 min_adll_per_pup[if_id][pup] = in ddr3_tip_pbs()
89 pup_state[if_id][pup] = 0x3; in ddr3_tip_pbs()
90 adll_shift_lock[if_id][pup] = 1; in ddr3_tip_pbs()
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Dddr3_training_hw_algo.c42 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) in ddr3_tip_write_additional_odt_setting() argument
53 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
56 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
59 val = data_read[if_id]; in ddr3_tip_write_additional_odt_setting()
75 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting()
99 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
103 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting()
111 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) in get_valid_win_rx() argument
124 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, in get_valid_win_rx()
160 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; in ddr3_tip_vref() local
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Dddr3_training_leveling.c22 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id,
24 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id,
29 u32 c_cs, if_id, bus_id; in ddr3_tip_max_cs_get() local
37 &if_id)); in ddr3_tip_max_cs_get()
45 interface_params[if_id].as_bus_params[bus_id]. in ddr3_tip_max_cs_get()
65 u32 bus_num, if_id, cl_val; in ddr3_tip_dynamic_read_leveling() local
79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
80 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
83 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
84 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
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Dddr3_training_centralization.c55 u32 if_id, pattern_id, bit_id; in ddr3_tip_centralization() local
79 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
80 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_centralization()
83 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
87 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization()
102 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_centralization()
103 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_centralization()
107 centralization_state[if_id][bus_id] = 0; in ddr3_tip_centralization()
108 bus_end_window[mode][if_id][bus_id] = in ddr3_tip_centralization()
110 bus_start_window[mode][if_id][bus_id] = 0; in ddr3_tip_centralization()
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Dddr3_debug.c111 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
119 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
120 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_reg_dump()
123 if_id, reg_addr, read_data, in ddr3_tip_reg_dump()
125 printf("0x%x ", read_data[if_id]); in ddr3_tip_reg_dump()
133 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_reg_dump()
134 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_reg_dump()
140 (dev_num, if_id, in ddr3_tip_reg_dump()
151 (dev_num, if_id, in ddr3_tip_reg_dump()
360 u32 if_id = 0; in ddr3_tip_print_log() local
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Dddr3_training.c92 u32 if_id, u32 cl_value, u32 cwl_value);
100 u32 if_id, enum hws_ddr_freq frequency);
102 u32 if_id, enum hws_ddr_freq frequency);
207 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
208 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
265 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
268 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
271 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
275 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
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Dddr3_training_ip_engine.c570 u32 if_id, enum hws_pattern pattern, in ddr3_tip_load_pattern_to_odpg() argument
582 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
588 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
595 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
601 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
608 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
614 (dev_num, access_type, if_id, in ddr3_tip_load_pattern_to_odpg()
624 u32 if_id, enum hws_dir direction, u32 tx_phases, in ddr3_tip_configure_odpg() argument
636 ret = ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_configure_odpg()
690 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, in ddr3_tip_read_training_result() argument
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Dddr3_training_ip_flow.h25 #define IS_IF_ACTIVE(if_mask, if_id) \ argument
26 ((if_mask) & (1 << (if_id)))
34 #define IS_BUS_ACTIVE(if_mask , if_id) \ argument
35 (((if_mask) >> (if_id)) & 1)
126 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
129 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
133 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
135 u32 if_id, u32 exp_value, u32 mask, u32 offset,
138 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
141 u32 if_id, u32 phy_id,
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Dddr3_training_ip_prv_if.h25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
38 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
56 u32 dev_num, enum hws_access_type access_type, u32 if_id,
68 enum hws_static_config_type static_config_type, u32 if_id);
70 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
72 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
81 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
Dddr3_training_bist.c13 u32 if_id,
73 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument
80 if (IS_IF_ACTIVE(tm->if_act_mask, if_id) == 0) in ddr3_tip_bist_read_result()
84 if_id)); in ddr3_tip_bist_read_result()
85 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
90 pst_bist_result->bist_fail_high = read_data[if_id]; in ddr3_tip_bist_read_result()
91 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
96 pst_bist_result->bist_fail_low = read_data[if_id]; in ddr3_tip_bist_read_result()
98 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result()
103 pst_bist_result->bist_last_fail_addr = read_data[if_id]; in ddr3_tip_bist_read_result()
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Dddr3_training_ip_engine.h41 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
63 u32 if_id,
76 u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id);
77 void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
Dmv_ddr_plat.c182 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
736 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, in ddr3_tip_a38x_set_divider() argument
743 if (if_id != 0) { in ddr3_tip_a38x_set_divider()
746 if_id)); in ddr3_tip_a38x_set_divider()
854 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_read() argument
868 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_write() argument
1374 u32 if_id, phy_id; in ddr3_tip_configure_phy() local
1412 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_configure_phy()
1414 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_configure_phy()
1423 if_id, phy_id, DDR_PHY_DATA, in ddr3_tip_configure_phy()
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Dddr3_init.c186 u32 if_id; in mv_ddr_training_params_set() local
191 &if_id)); in mv_ddr_training_params_set()
193 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num)); in mv_ddr_training_params_set()
Dddr3_training_hw_algo.h10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id);
Dddr3_training_leveling.h12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
Dddr3_init.h188 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num);
190 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
Dddr3_training_ip_bist.h35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
/external/u-boot/include/fsl-mc/
Dfsl_dprc.h346 MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
348 MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \
389 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \
412 MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
435 MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \
872 uint16_t if_id; member
/external/mesa3d/src/mesa/state_tracker/
Dst_glsl_to_tgsi_temprename.cpp618 int if_id = 0; in get_temp_registers_required_lifetimes() local
671 cur_scope = scopes.create(cur_scope, if_branch, if_id++, in get_temp_registers_required_lifetimes()