| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_combine_constants.cpp | 101 struct imm { struct
142 struct imm *imm; member
147 static struct imm *
151 if (table->imm[i].val == val) { in find_imm()
152 return &table->imm[i]; in find_imm()
158 static struct imm *
163 table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size); in new_imm()
165 return &table->imm[table->len++]; in new_imm()
179 const struct imm *a = (const struct imm *)_a, in compare()
180 *b = (const struct imm *)_b; in compare()
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| D | brw_reg.h | 587 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_DF); in brw_imm_df() local
588 imm.df = df; in brw_imm_df()
589 return imm; in brw_imm_df()
595 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F); in brw_imm_f() local
596 imm.f = f; in brw_imm_f()
597 return imm; in brw_imm_f()
604 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_Q); in brw_imm_q() local
605 imm.d64 = q; in brw_imm_q()
606 return imm; in brw_imm_q()
613 struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UQ); in brw_imm_uq() local
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| /external/clang/lib/Headers/ |
| D | avx512bwintrin.h | 1632 #define _mm512_shufflehi_epi16(A, imm) __extension__ ({ \ argument
1636 4 + (((imm) >> 0) & 0x3), \
1637 4 + (((imm) >> 2) & 0x3), \
1638 4 + (((imm) >> 4) & 0x3), \
1639 4 + (((imm) >> 6) & 0x3), \
1641 12 + (((imm) >> 0) & 0x3), \
1642 12 + (((imm) >> 2) & 0x3), \
1643 12 + (((imm) >> 4) & 0x3), \
1644 12 + (((imm) >> 6) & 0x3), \
1646 20 + (((imm) >> 0) & 0x3), \
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| D | avx2intrin.h | 498 #define _mm256_shuffle_epi32(a, imm) __extension__ ({ \ argument
501 0 + (((imm) >> 0) & 0x3), \
502 0 + (((imm) >> 2) & 0x3), \
503 0 + (((imm) >> 4) & 0x3), \
504 0 + (((imm) >> 6) & 0x3), \
505 4 + (((imm) >> 0) & 0x3), \
506 4 + (((imm) >> 2) & 0x3), \
507 4 + (((imm) >> 4) & 0x3), \
508 4 + (((imm) >> 6) & 0x3)); })
510 #define _mm256_shufflehi_epi16(a, imm) __extension__ ({ \ argument
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| D | emmintrin.h | 1102 #define _mm_slli_si128(a, imm) __extension__ ({ \ argument
1106 ((char)(imm)&0xF0) ? 0 : 16 - (char)(imm), \
1107 ((char)(imm)&0xF0) ? 1 : 17 - (char)(imm), \
1108 ((char)(imm)&0xF0) ? 2 : 18 - (char)(imm), \
1109 ((char)(imm)&0xF0) ? 3 : 19 - (char)(imm), \
1110 ((char)(imm)&0xF0) ? 4 : 20 - (char)(imm), \
1111 ((char)(imm)&0xF0) ? 5 : 21 - (char)(imm), \
1112 ((char)(imm)&0xF0) ? 6 : 22 - (char)(imm), \
1113 ((char)(imm)&0xF0) ? 7 : 23 - (char)(imm), \
1114 ((char)(imm)&0xF0) ? 8 : 24 - (char)(imm), \
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoC.td | 214 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
215 OpcodeStr, "$rd, ${imm}(${rs1})">;
220 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
221 OpcodeStr, "$rs2, ${imm}(${rs1})">;
226 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
227 OpcodeStr, "$rd, ${imm}(${rs1})">;
232 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
233 OpcodeStr, "$rs2, ${imm}(${rs1})">;
238 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
239 OpcodeStr, "$rs1, $imm"> {
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| /external/v8/src/wasm/ |
| D | function-body-decoder-impl.h | 380 const BranchTableImmediate<validate>& imm) in BranchTableIterator() argument
382 start_(imm.start), in BranchTableIterator()
383 pc_(imm.table), in BranchTableIterator()
384 table_count_(imm.table_count) {} in BranchTableIterator()
628 F(GetLocal, Value* result, const LocalIndexImmediate<validate>& imm) \
629 F(SetLocal, const Value& value, const LocalIndexImmediate<validate>& imm) \
631 const LocalIndexImmediate<validate>& imm) \
632 F(GetGlobal, Value* result, const GlobalIndexImmediate<validate>& imm) \
633 F(SetGlobal, const Value& value, const GlobalIndexImmediate<validate>& imm) \
639 F(BrTable, const BranchTableImmediate<validate>& imm, const Value& key) \
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| D | wasm-text.cc | 103 BlockTypeImmediate<Decoder::kNoValidate> imm(kAllWasmFeatures, &i, in PrintWasmText() local
106 if (imm.type == kWasmVar) { in PrintWasmText()
107 os << " (type " << imm.sig_index << ")"; in PrintWasmText()
108 } else if (imm.out_arity() > 0) { in PrintWasmText()
109 os << " " << ValueTypes::TypeName(imm.out_type(0)); in PrintWasmText()
116 BreakDepthImmediate<Decoder::kNoValidate> imm(&i, i.pc()); in PrintWasmText() local
117 os << WasmOpcodes::OpcodeName(opcode) << ' ' << imm.depth; in PrintWasmText()
128 BranchTableImmediate<Decoder::kNoValidate> imm(&i, i.pc()); in PrintWasmText() local
129 BranchTableIterator<Decoder::kNoValidate> iterator(&i, imm); in PrintWasmText()
135 CallIndirectImmediate<Decoder::kNoValidate> imm(&i, i.pc()); in PrintWasmText() local
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| /external/vixl/src/aarch32/ |
| D | instructions-aarch32.cc | 605 ImmediateT32::ImmediateT32(uint32_t imm) { in ImmediateT32() argument
607 if ((imm & ~0xff) == 0) { in ImmediateT32()
608 SetEncodingValue(imm); in ImmediateT32()
611 if ((imm >> 16) == (imm & 0xffff)) { in ImmediateT32()
612 if ((imm & 0xff00) == 0) { in ImmediateT32()
614 SetEncodingValue((imm & 0xff) | (0x1 << 8)); in ImmediateT32()
617 if ((imm & 0xff) == 0) { in ImmediateT32()
619 SetEncodingValue(((imm >> 8) & 0xff) | (0x2 << 8)); in ImmediateT32()
622 if (((imm >> 8) & 0xff) == (imm & 0xff)) { in ImmediateT32()
624 SetEncodingValue((imm & 0xff) | (0x3 << 8)); in ImmediateT32()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrMemory.td | 83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
84 (LOAD_I32 imm:$off, $addr, 0)>;
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
86 (LOAD_I64 imm:$off, $addr, 0)>;
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
88 (LOAD_F32 imm:$off, $addr, 0)>;
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
90 (LOAD_F64 imm:$off, $addr, 0)>;
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
92 (LOAD_I32 imm:$off, $addr, 0)>;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 26 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
29 llvm_i32_ty, // inst_offset(imm)
30 llvm_i32_ty, // dfmt(imm)
31 llvm_i32_ty, // nfmt(imm)
32 llvm_i32_ty, // offen(imm)
33 llvm_i32_ty, // idxen(imm)
34 llvm_i32_ty, // glc(imm)
35 llvm_i32_ty, // slc(imm)
36 llvm_i32_ty], // tfe(imm)
45 llvm_i32_ty, // inst_offset(imm)
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrAliases.td | 66 // b<cond> $imm
67 def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
68 (BCOND brtarget:$imm, condVal)>;
70 // b<cond>,a $imm
71 def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
72 (BCONDA brtarget:$imm, condVal)>;
74 // b<cond> %icc, $imm
75 def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
78 // b<cond>,pt %icc, $imm
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| /external/capstone/arch/Mips/ |
| D | MipsInstPrinter.c | 206 int64_t imm = MCOperand_getImm(Op); in printOperand() local
208 if (imm) { // only print Imm offset if it is not 0 in printOperand()
209 if (imm >= 0) { in printOperand()
210 if (imm > HEX_THRESHOLD) in printOperand()
211 SStream_concat(O, "0x%"PRIx64, imm); in printOperand()
213 SStream_concat(O, "%"PRIu64, imm); in printOperand()
215 if (imm < -HEX_THRESHOLD) in printOperand()
216 SStream_concat(O, "-0x%"PRIx64, -imm); in printOperand()
218 SStream_concat(O, "-%"PRIu64, -imm); in printOperand()
222 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm; in printOperand()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativePPC_32.c | 29 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
31 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
32 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
34 if (!(imm & ~0xffff)) in load_immediate()
35 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
37 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
38 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
109 return push_inst(compiler, ADDIS | D(dst) | A(src1) | compiler->imm); in emit_single_op()
112 …h_inst(compiler, ADDIS | D(dst) | A(src1) | (((compiler->imm >> 16) & 0xffff) + ((compiler->imm >>… in emit_single_op()
116 return push_inst(compiler, ADDI | D(dst) | A(src1) | (compiler->imm & 0xffff)); in emit_single_op()
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| D | sljitNativePPC_64.c | 44 static sljit_s32 load_immediate(struct sljit_compiler *compiler, sljit_s32 reg, sljit_sw imm) in load_immediate() argument
51 if (imm <= SIMM_MAX && imm >= SIMM_MIN) in load_immediate()
52 return push_inst(compiler, ADDI | D(reg) | A(0) | IMM(imm)); in load_immediate()
54 if (!(imm & ~0xffff)) in load_immediate()
55 return push_inst(compiler, ORI | S(TMP_ZERO) | A(reg) | IMM(imm)); in load_immediate()
57 if (imm <= 0x7fffffffl && imm >= -0x80000000l) { in load_immediate()
58 FAIL_IF(push_inst(compiler, ADDIS | D(reg) | A(0) | IMM(imm >> 16))); in load_immediate()
59 return (imm & 0xffff) ? push_inst(compiler, ORI | S(reg) | A(reg) | IMM(imm)) : SLJIT_SUCCESS; in load_immediate()
63 tmp = (imm >= 0) ? imm : ~imm; in load_immediate()
67 tmp = (imm << shift); in load_immediate()
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| D | sljitNativeARM_T2_32.c | 64 #define IMM3(imm) (imm << 6) argument
65 #define IMM8(imm) (imm) argument
83 #define IMM5(imm) \ argument
84 (COPY_BITS(imm, 2, 12, 3) | ((imm & 0x3) << 6))
85 #define IMM12(imm) \ argument
86 (COPY_BITS(imm, 11, 26, 1) | COPY_BITS(imm, 8, 12, 3) | (imm & 0xff))
222 …JIT_INLINE sljit_s32 emit_imm32_const(struct sljit_compiler *compiler, sljit_s32 dst, sljit_uw imm) in emit_imm32_const() argument
225 …| COPY_BITS(imm, 12, 16, 4) | COPY_BITS(imm, 11, 26, 1) | COPY_BITS(imm, 8, 12, 3) | (imm & 0xff))… in emit_imm32_const()
227 …| COPY_BITS(imm, 12 + 16, 16, 4) | COPY_BITS(imm, 11 + 16, 26, 1) | COPY_BITS(imm, 8 + 16, 12, 3) … in emit_imm32_const()
474 static sljit_uw get_imm(sljit_uw imm) in get_imm() argument
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 24 llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
27 llvm_i32_ty, // inst_offset(imm)
28 llvm_i32_ty, // dfmt(imm)
29 llvm_i32_ty, // nfmt(imm)
30 llvm_i32_ty, // offen(imm)
31 llvm_i32_ty, // idxen(imm)
32 llvm_i32_ty, // glc(imm)
33 llvm_i32_ty, // slc(imm)
34 llvm_i32_ty], // tfe(imm)
43 llvm_i32_ty, // inst_offset(imm)
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 67 def i64immSExt32 : PatLeaf<(i64 imm),
69 def i32immSExt32 : PatLeaf<(i32 imm),
85 def BPF_CC_EQ : PatLeaf<(i64 imm),
87 def BPF_CC_NE : PatLeaf<(i64 imm),
89 def BPF_CC_GE : PatLeaf<(i64 imm),
91 def BPF_CC_GT : PatLeaf<(i64 imm),
93 def BPF_CC_GTU : PatLeaf<(i64 imm),
95 def BPF_CC_GEU : PatLeaf<(i64 imm),
97 def BPF_CC_LE : PatLeaf<(i64 imm),
99 def BPF_CC_LT : PatLeaf<(i64 imm),
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | bitreverse.ll | 17 ; X86-NEXT: andl $3855, %edx # imm = 0xF0F
19 ; X86-NEXT: andl $61680, %eax # imm = 0xF0F0
23 ; X86-NEXT: andl $13107, %edx # imm = 0x3333
24 ; X86-NEXT: andl $52428, %eax # imm = 0xCCCC
28 ; X86-NEXT: andl $21845, %edx # imm = 0x5555
29 ; X86-NEXT: andl $43690, %eax # imm = 0xAAAA
34 ; X86-NEXT: andl $3855, %edx # imm = 0xF0F
36 ; X86-NEXT: andl $61680, %ecx # imm = 0xF0F0
40 ; X86-NEXT: andl $13107, %edx # imm = 0x3333
41 ; X86-NEXT: andl $52428, %ecx # imm = 0xCCCC
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonDepOperands.td | 15 def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>;
18 def s29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
21 def s10_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 6>(N->getSExtValue());}]>;
24 def u6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>;
27 def a30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
30 def u29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>;
33 def s8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<8, 0>(N->getSExtValue());}]>;
36 def u32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>;
39 def u4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>;
42 def u3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>;
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| /external/capstone/arch/X86/ |
| D | X86ATTInstPrinter.c | 252 int64_t imm = MCOperand_getImm(Op); in _printOperand() local
253 if (imm < 0) { in _printOperand()
254 if (imm < -HEX_THRESHOLD) in _printOperand()
255 SStream_concat(O, "$-0x%"PRIx64, -imm); in _printOperand()
257 SStream_concat(O, "$-%"PRIu64, -imm); in _printOperand()
259 if (imm > HEX_THRESHOLD) in _printOperand()
260 SStream_concat(O, "$0x%"PRIx64, imm); in _printOperand()
262 SStream_concat(O, "$%"PRIu64, imm); in _printOperand()
408 int64_t imm = MCOperand_getImm(DispSpec); in printMemOffset() local
410 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; in printMemOffset()
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| D | X86IntelInstPrinter.c | 277 int64_t imm = MCOperand_getImm(Op); in _printOperand() local
278 if (imm < 0) { in _printOperand()
279 if (imm < -HEX_THRESHOLD) in _printOperand()
280 SStream_concat(O, "-0x%"PRIx64, -imm); in _printOperand()
282 SStream_concat(O, "-%"PRIu64, -imm); in _printOperand()
285 if (imm > HEX_THRESHOLD) in _printOperand()
286 SStream_concat(O, "0x%"PRIx64, imm); in _printOperand()
288 SStream_concat(O, "%"PRIu64, imm); in _printOperand()
439 int64_t imm = MCOperand_getImm(DispSpec); in printMemOffset() local
441 MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; in printMemOffset()
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| /external/iproute2/include/ |
| D | bpf_util.h | 76 .imm = 0 })
84 .imm = 0 })
94 .imm = IMM })
102 .imm = IMM })
112 .imm = 0 })
120 .imm = 0 })
130 .imm = IMM })
138 .imm = IMM })
150 .imm = (__u32) (IMM) }), \
156 .imm = ((__u64) (IMM)) >> 32 })
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| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/ |
| D | mblaze_imm.txt | 55 # CHECK: imm 0
59 # CHECK: imm 1
63 # CHECK: imm 2
67 # CHECK: imm 4
71 # CHECK: imm 8
75 # CHECK: imm 16
79 # CHECK: imm 32
83 # CHECK: imm 64
87 # CHECK: imm 128
91 # CHECK: imm 256
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