| /external/vixl/src/aarch32/ |
| D | disasm-aarch32.cc | 31185 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31189 imm6; in DecodeT32()
31215 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31219 imm6; in DecodeT32()
31245 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31249 imm6; in DecodeT32()
31275 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31279 imm6; in DecodeT32()
31464 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31468 imm6; in DecodeT32()
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| D | assembler-aarch32.cc | 23306 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local
23310 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn()
23329 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local
23332 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn()
23358 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local
23361 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun()
23379 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local
23382 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun()
23442 uint32_t imm6 = imm; in vqshl() local
23446 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqshl()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3135 let Inst{21-19} = 0b001; // imm6 = 001xxx
3139 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3143 let Inst{21} = 0b1; // imm6 = 1xxxxx
3147 // imm6 = xxxxxx
3152 let Inst{21-19} = 0b001; // imm6 = 001xxx
3156 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3160 let Inst{21} = 0b1; // imm6 = 1xxxxx
3164 // imm6 = xxxxxx
3172 let Inst{21-19} = 0b001; // imm6 = 001xxx
3176 let Inst{21-20} = 0b01; // imm6 = 01xxxx
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| D | ARMInstrFormats.td | 197 // other shift immediates. The imm6 field is encoded like so:
200 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
201 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
202 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
203 // 64 64 - <imm> is encoded in imm6<5:0>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3884 let Inst{21-19} = 0b001; // imm6 = 001xxx
3888 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3892 let Inst{21} = 0b1; // imm6 = 1xxxxx
3896 // imm6 = xxxxxx
3901 let Inst{21-19} = 0b001; // imm6 = 001xxx
3905 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3909 let Inst{21} = 0b1; // imm6 = 1xxxxx
3913 // imm6 = xxxxxx
3921 let Inst{21-19} = 0b001; // imm6 = 001xxx
3925 let Inst{21-20} = 0b01; // imm6 = 01xxxx
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| D | ARMInstrFormats.td | 217 // other shift immediates. The imm6 field is encoded like so:
220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
223 // 64 64 - <imm> is encoded in imm6<5:0>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3975 let Inst{21-19} = 0b001; // imm6 = 001xxx
3979 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3983 let Inst{21} = 0b1; // imm6 = 1xxxxx
3987 // imm6 = xxxxxx
3992 let Inst{21-19} = 0b001; // imm6 = 001xxx
3996 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4000 let Inst{21} = 0b1; // imm6 = 1xxxxx
4004 // imm6 = xxxxxx
4012 let Inst{21-19} = 0b001; // imm6 = 001xxx
4016 let Inst{21-20} = 0b01; // imm6 = 01xxxx
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| D | ARMInstrFormats.td | 220 // other shift immediates. The imm6 field is encoded like so:
223 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
224 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
225 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
226 // 64 64 - <imm> is encoded in imm6<5:0>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 1444 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
1445 asm, "\t$Rd, $Rn, $imm6",
1450 bits<6> imm6;
1456 let Inst{10-5} = imm6;
1461 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
1462 asm, "\t$Rd, $imm6",
1466 bits<6> imm6;
1472 let Inst{10-5} = imm6;
3615 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
3616 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
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| D | AArch64InstrFormats.td | 780 // {5-0} - imm6
802 // {5-0} - imm6
824 // {5-0} - imm6: #0, #8, #16, or #24
833 // {5-0} - imm6: #0 or #8
863 // {5-0} - imm6: #0 or #12
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 4520 int imm6 = 0; in EncodeNeonShiftOp() local
4526 imm6 = size_in_bits + shift; in EncodeNeonShiftOp()
4532 imm6 = 2 * size_in_bits - shift; in EncodeNeonShiftOp()
4538 imm6 = size_in_bits + shift; in EncodeNeonShiftOp()
4539 int L = imm6 >> 6; in EncodeNeonShiftOp()
4540 imm6 &= 0x3F; in EncodeNeonShiftOp()
4546 imm6 = 2 * size_in_bits - shift; in EncodeNeonShiftOp()
4547 int L = imm6 >> 6; in EncodeNeonShiftOp()
4548 imm6 &= 0x3F; in EncodeNeonShiftOp()
4562 return 0x1E5U * B23 | d * B22 | imm6 * B16 | vd * B12 | m * B5 | B4 | vm | in EncodeNeonShiftOp()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 357 # imm6=0b0xxxxx -> UNDEFINED
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | invalid-armv7.txt | 357 # imm6=0b0xxxxx -> UNDEFINED
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 183 // Addressing mode pattern reg+imm6
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 217 // Addressing mode pattern reg+imm6
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 574 // {5-0} - imm6
596 // {5-0} - imm6
618 // {5-0} - imm6: #0, #8, #16, or #24
627 // {5-0} - imm6: #0 or #8
655 // {5-0} - imm6: #0 or #12
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 5437 // op: imm6
6241 // op: imm6
8341 // op: imm6
9441 // op: imm6
|