| /external/vixl/test/aarch32/config/ |
| D | cond-sp-sp-operand-imm7-t32.json | 28 // MNEMONIC{<c>}.N <Rd>, SP #<imm7>
32 "Add", // ADD{<c>}{<q>} {SP}, SP, #<imm7> ; T2
33 "Sub" // SUB{<c>}{<q>} {SP}, SP, #<imm7> ; T1
|
| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 1050 Instr Assembler::ImmLSPair(int imm7, unsigned size) {
1051 DCHECK_EQ((imm7 >> size) << size, imm7);
1052 int scaled_imm7 = imm7 >> size;
1076 Instr Assembler::ImmHint(int imm7) {
1077 DCHECK(is_uint7(imm7));
1078 return imm7 << ImmHint_offset;
|
| D | assembler-arm64.h | 2970 inline static Instr ImmLSPair(int imm7, unsigned size);
2974 inline static Instr ImmHint(int imm7);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | README.txt | 82 | Ks7 | imm7 | |
83 | KN7 | -imm7 | |
|
| D | BlackfinInstrInfo.td | 82 def imm7 : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
191 [(set DP:$dst, imm7:$src)]>;
754 [(set D:$dst, (add D:$src1, imm7:$src2))]>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 646 unsigned imm7 = 0; in DecodeTRAP() local
648 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
659 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
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| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 644 unsigned imm7 = 0; in DecodeTRAP() local
646 imm7 = fieldFromInstruction(insn, 0, 7); in DecodeTRAP()
657 MI.addOperand(MCOperand::createImm(imm7)); in DecodeTRAP()
|
| /external/v8/src/arm/ |
| D | disasm-arm.cc | 2387 int imm7 = instr->Bits(21, 16); in DecodeSpecialCondition() local
2388 if (instr->Bit(7) != 0) imm7 += 64; in DecodeSpecialCondition()
2389 int size = base::bits::RoundDownToPowerOfTwo32(imm7); in DecodeSpecialCondition()
2393 shift = imm7 - size; in DecodeSpecialCondition()
2396 shift = 2 * size - imm7; in DecodeSpecialCondition()
|
| D | simulator-arm.cc | 5357 int imm7 = instr->Bits(21, 16); in DecodeSpecialCondition() local
5358 if (instr->Bit(7) != 0) imm7 += 64; in DecodeSpecialCondition()
5359 int size = base::bits::RoundDownToPowerOfTwo32(imm7); in DecodeSpecialCondition()
5360 int shift = imm7 - size; in DecodeSpecialCondition()
5383 int imm7 = instr->Bits(21, 16); in DecodeSpecialCondition() local
5384 if (instr->Bit(7) != 0) imm7 += 64; in DecodeSpecialCondition()
5385 int size = base::bits::RoundDownToPowerOfTwo32(imm7); in DecodeSpecialCondition()
5386 int shift = 2 * size - imm7; in DecodeSpecialCondition()
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2124 void hint(int imm7);
3735 static Instr ImmLSPair(int64_t imm7, unsigned access_size) { in ImmLSPair() argument
3736 VIXL_ASSERT(IsMultiple(imm7, 1 << access_size)); in ImmLSPair()
3737 int64_t scaled_imm7 = imm7 / (1 << access_size); in ImmLSPair()
3762 static Instr ImmHint(int imm7) { in ImmHint() argument
3763 VIXL_ASSERT(IsUint7(imm7)); in ImmHint()
3764 return imm7 << ImmHint_offset; in ImmHint()
|
| D | macro-assembler-aarch64.h | 1596 void Hint(int imm7) { in Hint() argument
1599 hint(imm7); in Hint()
|
| D | assembler-aarch64.cc | 1782 void Assembler::hint(int imm7) { in hint() argument
1783 VIXL_ASSERT(IsUint7(imm7)); in hint()
1784 Emit(HINT | ImmHint(imm7) | Rt(xzr)); in hint()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 327 // ADD sp, sp, #<imm7>
337 // SUB sp, sp, #<imm7>
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 389 // ADD sp, sp, #<imm7>
399 // SUB sp, sp, #<imm7>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 406 // ADD sp, sp, #<imm7>
416 // SUB sp, sp, #<imm7>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | SVEInstrFormats.td | 2182 : I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
2183 asm, "\t$Pd, $Pg/z, $Zn, $imm7",
2189 bits<7> imm7;
2193 let Inst{20-14} = imm7;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 4869 // op: imm7
|