| /external/capstone/arch/AArch64/ |
| D | AArch64AddressingModes.h | 132 unsigned imms = val & 0x3f; in AArch64_AM_decodeLogicalImmediate() local
136 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in AArch64_AM_decodeLogicalImmediate()
140 unsigned S = imms & (size - 1); in AArch64_AM_decodeLogicalImmediate()
165 unsigned imms = val & 0x3f; in AArch64_AM_isValidDecodeLogicalImmediate() local
169 len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in AArch64_AM_isValidDecodeLogicalImmediate()
173 S = imms & (size - 1); in AArch64_AM_isValidDecodeLogicalImmediate()
|
| D | AArch64InstPrinter.c | 140 int64_t imms = MCOperand_getImm(Op3); in AArch64_printInst() local
142 if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in AArch64_printInst()
144 shift = 31 - imms; in AArch64_printInst()
145 } else if (Opcode == AArch64_UBFMXri && imms != 0x3f && in AArch64_printInst()
146 ((imms + 1 == immr))) { in AArch64_printInst()
148 shift = 63 - imms; in AArch64_printInst()
149 } else if (Opcode == AArch64_UBFMWri && imms == 0x1f) { in AArch64_printInst()
152 } else if (Opcode == AArch64_UBFMXri && imms == 0x3f) { in AArch64_printInst()
155 } else if (Opcode == AArch64_SBFMWri && imms == 0x1f) { in AArch64_printInst()
158 } else if (Opcode == AArch64_SBFMXri && imms == 0x3f) { in AArch64_printInst()
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_dataflow_swizzles.c | 106 float imms[4] = {0.0f, 0.0f, 0.0f, 0.0f}; in try_rewrite_constant() local
389 imms[new_swz] = 0.0f; in try_rewrite_constant()
393 imms[new_swz] = -0.5f; in try_rewrite_constant()
395 imms[new_swz] = 0.5f; in try_rewrite_constant()
400 imms[new_swz] = -1.0f; in try_rewrite_constant()
402 imms[new_swz] = 1.0f; in try_rewrite_constant()
406 imms[new_swz] = rc_get_constant_value(c, reg->Index, in try_rewrite_constant()
412 imms); in try_rewrite_constant()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/relax-mem/ |
| D | STDWPtrQRr.mir | 18 ; We shouldn't expand things which already have 6-bit imms.
22 ; We shouldn't expand things which already have 6-bit imms.
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 296 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
299 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in decodeLogicalImmediate()
303 unsigned S = imms & (size - 1); in decodeLogicalImmediate()
324 unsigned imms = val & 0x3f; in isValidDecodeLogicalImmediate() local
328 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in isValidDecodeLogicalImmediate()
332 unsigned S = imms & (size - 1); in isValidDecodeLogicalImmediate()
|
| /external/mesa3d/src/gallium/auxiliary/translate/ |
| D | translate_sse.c | 473 unsigned imms[2] = { 0, 0x3f800000 }; in translate_attr_convert() local
682 imms[swizzle[0] - PIPE_SWIZZLE_0]); in translate_attr_convert()
692 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
710 imms[swizzle[2] - PIPE_SWIZZLE_0]); in translate_attr_convert()
720 imms[swizzle[3] - PIPE_SWIZZLE_0]); in translate_attr_convert()
742 unsigned imms[2] = { 0, 1 }; in translate_attr_convert() local
798 imms[1] = in translate_attr_convert()
826 imms[swizzle[1] - PIPE_SWIZZLE_0]); in translate_attr_convert()
833 (imms[swizzle[1] - PIPE_SWIZZLE_0] << 16) | in translate_attr_convert()
834 imms[swizzle[0] - PIPE_SWIZZLE_0]); in translate_attr_convert()
[all …]
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_build_util.cpp | 47 memset(imms, 0, sizeof(imms)); in init()
59 while (imms[pos]) in addImmediate()
61 imms[pos] = imm; in addImmediate()
361 while (imms[pos] && imms[pos]->reg.data.u32 != u) in mkImm()
364 ImmediateValue *imm = imms[pos]; in mkImm()
|
| D | nv50_ir_build_util.h | 192 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 297 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
300 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in decodeLogicalImmediate()
304 unsigned S = imms & (size - 1); in decodeLogicalImmediate()
325 unsigned imms = val & 0x3f; in isValidDecodeLogicalImmediate() local
329 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in isValidDecodeLogicalImmediate()
333 unsigned S = imms & (size - 1); in isValidDecodeLogicalImmediate()
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 114 int64_t imms = Op3.getImm(); in printInst() local
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
117 shift = 31 - imms; in printInst()
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
119 ((imms + 1 == immr))) { in printInst()
121 shift = 63 - imms; in printInst()
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
131 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { in printInst()
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_tgsi_setup.c | 535 ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle], in si_llvm_emit_fetch()
538 ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle + 1], in si_llvm_emit_fetch()
542 return LLVMConstBitCast(ctx->imms[reg->Register.Index * TGSI_NUM_CHANNELS + swizzle], ctype); in si_llvm_emit_fetch()
990 ctx->imms[ctx->imms_num * TGSI_NUM_CHANNELS + i] = in emit_immediate()
1116 FREE(ctx->imms); in si_llvm_context_set_tgsi()
1117 ctx->imms = NULL; in si_llvm_context_set_tgsi()
1138 ctx->imms = MALLOC(size * TGSI_NUM_CHANNELS * sizeof(LLVMValueRef)); in si_llvm_context_set_tgsi()
1274 FREE(ctx->imms); in si_llvm_dispose()
1275 ctx->imms = NULL; in si_llvm_dispose()
|
| D | si_shader_internal.h | 94 LLVMValueRef *imms; member
|
| D | si_shader_tgsi_mem.c | 1592 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]); in tex_fetch_args()
1602 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]); in tex_fetch_args()
1610 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]); in tex_fetch_args()
1635 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX]; in tex_fetch_args()
|
| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 956 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
957 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
958 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
960 return imms << ImmS_offset;
973 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
975 DCHECK(is_uint6(imms));
976 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
978 return imms << ImmSetBits_offset;
|
| D | assembler-arm64.h | 1364 void bfm(const Register& rd, const Register& rn, int immr, int imms);
1367 void sbfm(const Register& rd, const Register& rn, int immr, int imms);
1370 void ubfm(const Register& rd, const Register& rn, int immr, int imms);
2947 inline static Instr ImmS(unsigned imms, unsigned reg_size);
2949 inline static Instr ImmSetBits(unsigned imms, unsigned reg_size);
|
| D | assembler-arm64.cc | 1304 int imms) { in bfm() argument
1309 ImmS(imms, rn.SizeInBits()) | in bfm()
1315 int imms) { in sbfm() argument
1320 ImmS(imms, rn.SizeInBits()) | in sbfm()
1326 int imms) { in ubfm() argument
1331 ImmS(imms, rn.SizeInBits()) | in ubfm()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 123 int64_t imms = Op3.getImm(); in printInst() local
124 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
126 shift = 31 - imms; in printInst()
127 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
128 ((imms + 1 == immr))) { in printInst()
130 shift = 63 - imms; in printInst()
131 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
134 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
137 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
140 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { in printInst()
|
| /external/v8/src/compiler/ia32/ |
| D | instruction-selector-ia32.cc | 2421 uint32_t imms[kMaxImms]; in VisitS8x16Shuffle() local
2447 imms[imm_count++] = offset; in VisitS8x16Shuffle()
2469 imms[imm_count++] = shuffle_mask; in VisitS8x16Shuffle()
2477 imms[imm_count++] = blend_mask; in VisitS8x16Shuffle()
2482 imms[imm_count++] = shuffle_mask; in VisitS8x16Shuffle()
2484 imms[imm_count++] = blend_mask; in VisitS8x16Shuffle()
2492 imms[imm_count++] = blend_mask; in VisitS8x16Shuffle()
2496 imms[imm_count++] = index; in VisitS8x16Shuffle()
2504 imms[imm_count++] = mask_lo; in VisitS8x16Shuffle()
2505 imms[imm_count++] = mask_hi; in VisitS8x16Shuffle()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 728 unsigned imms);
734 unsigned imms);
740 unsigned imms);
3655 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument
3656 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || in ImmS()
3657 ((reg_size == kWRegSize) && IsUint5(imms))); in ImmS()
3659 return imms << ImmS_offset; in ImmS()
3670 static Instr ImmSetBits(unsigned imms, unsigned reg_size) { in ImmSetBits() argument
3672 VIXL_ASSERT(IsUint6(imms)); in ImmSetBits()
3673 VIXL_ASSERT((reg_size == kXRegSize) || IsUint6(imms + 3)); in ImmSetBits()
[all …]
|
| D | macro-assembler-aarch64.h | 1021 unsigned imms) { in Bfm() argument
1026 bfm(rd, rn, immr, imms); in Bfm()
2149 unsigned imms) { in Sbfm() argument
2154 sbfm(rd, rn, immr, imms); in Sbfm()
2426 unsigned imms) { in Ubfm() argument
2431 ubfm(rd, rn, immr, imms); in Ubfm()
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_soa.c | 2920 LLVMValueRef imms[4]; in lp_emit_immediate_soa() local
2927 imms[i] = in lp_emit_immediate_soa()
2937 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
2944 imms[i] = LLVMConstBitCast(tmp, bld_base->base.vec_type); in lp_emit_immediate_soa()
2950 imms[i] = bld_base->base.undef; in lp_emit_immediate_soa()
2963 LLVMBuildStore(builder, imms[i], imm_ptr); in lp_emit_immediate_soa()
2972 bld->immediates[bld->num_immediates][i] = imms[i]; in lp_emit_immediate_soa()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | arm-cgp-phis-calls-ret.ll | 4 …-arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileChe…
|
| D | arm-cgp-icmps.ll | 3 …-arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileChe…
|