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Searched refs:in_be32 (Results 1 – 25 of 225) sorted by relevance

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/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfsl_lsch2_serdes.c180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
206 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
216 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
222 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
231 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
234 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
240 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
243 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dimmap.c27 in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr)); in do_siuinfo()
28 printf("SWT = %08x\n", in_be32(&sc->sc_swt)); in do_siuinfo()
30 in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask)); in do_siuinfo()
32 in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec)); in do_siuinfo()
34 in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr)); in do_siuinfo()
49 i, in_be32(p), i, in_be32(p + 1)); in do_memcinfo()
51 printf("MAR = %08x", in_be32(&memctl->memc_mar)); in do_memcinfo()
52 printf(" MCR = %08x\n", in_be32(&memctl->memc_mcr)); in do_memcinfo()
54 in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); in do_memcinfo()
57 in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr)); in do_memcinfo()
[all …]
/external/u-boot/arch/m68k/cpu/mcf5445x/
Dspeed.c65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
92 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
97 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
106 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
112 pdr = in_be32(&pll->pdr); in setup_5441x_clocks()
171 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; in setup_5445x_clocks()
186 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; in setup_5445x_clocks()
188 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) in setup_5445x_clocks()
199 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in setup_5445x_clocks()
202 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; in setup_5445x_clocks()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dmpc8536_serdes.c93 u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); in fsl_serdes_init()
115 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
122 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
127 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
134 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
143 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
148 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
153 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
158 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
165 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
[all …]
Dfsl_corenet2_serdes.c124 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane()
211 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
224 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); in serdes_init()
231 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
266 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
275 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
283 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
293 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
302 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
305 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
[all …]
Dspeed.c83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT in get_sys_info()
95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> in get_sys_info()
112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in get_sys_info()
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
178 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) in get_sys_info()
189 u32 c_pll_sel = (in_be32 in get_sys_info()
214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; in get_sys_info()
216 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()
[all …]
Dcpu_init.c83 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); in fsl_erratum_a006261_workaround()
92 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); in fsl_erratum_a006261_workaround()
102 u32 status = in_be32(&usb_phy->status1); in fsl_erratum_a006261_workaround()
118 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); in fsl_erratum_a006261_workaround()
121 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp); in fsl_erratum_a006261_workaround()
224 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { in disable_cpc_sram()
300 cpccfg0 = in_be32(&cpc->cpccfg0); in enable_cpc()
321 in_be32(&cpc->cpccsr0); in enable_cpc()
336 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) in invalidate_cpc()
340 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) in invalidate_cpc()
[all …]
Dfsl_corenet_serdes.c114 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
127 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); in serdes_lane_enabled()
135 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) in is_serdes_configured()
171 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) in serdes_get_first_lane()
174 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; in serdes_get_first_lane()
253 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) in serdes_reset_rx()
257 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; in serdes_reset_rx()
297 rcw5 = in_be32(gur->rcwsr + 5); in enable_bank()
384 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; in p4080_erratum_serdes8()
472 rstctl = in_be32(&srds_regs->bank[bank].rstctl); in wait_for_rstdone()
[all …]
Dmp.c50 (void)in_be32(&pic->pir); in cpu_reset()
93 u32 coredisrl = in_be32(&gur->coredisrl); in is_core_disabled()
119 u32 devdisr = in_be32(&gur->devdisr); in is_core_disabled()
266 whoami = in_be32(&pic->whoami); in plat_mp_up()
278 in_be32(&ccm->bstrar); in plat_mp_up()
309 in_be32(&rcpm->ctbenrl); in plat_mp_up()
339 whoami = in_be32(&pic->whoami); in plat_mp_up()
343 devdisr = in_be32(&gur->devdisr); in plat_mp_up()
352 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
385 in_be32(&gur->devdisr); in plat_mp_up()
Dqe_io.c33 in_be32(&par_io[port].cpdir2) : in qe_config_iopin()
34 in_be32(&par_io[port].cpdir1); in qe_config_iopin()
48 tmp_val = in_be32(&par_io[port].cpodr); in qe_config_iopin()
56 in_be32(&par_io[port].cppar2): in qe_config_iopin()
57 in_be32(&par_io[port].cppar1); in qe_config_iopin()
Dcmd_errata.c41 if (in_be32(dcsr + offsets[i]) != 2) { in check_erratum_a4849()
62 if (in_be32(dcsr + 0x108) != x108) { in check_erratum_a4849()
100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || in check_erratum_a4580()
101 (in_be32(&srds_lane->res4[1]) != 0x880000) || in check_erratum_a4580()
102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { in check_erratum_a4580()
124 if (in_be32(plldgdcr) & 0x1fe) { in check_erratum_a007212()
/external/u-boot/drivers/ddr/fsl/
Dmpc85xx_ddr_gen3.c209 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
210 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
217 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
231 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
251 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
271 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
291 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
311 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
324 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
346 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) in fsl_ddr_set_memctl_regs()
[all …]
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dserdes.c53 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
58 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
67 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
80 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
85 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
103 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
108 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
125 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
130 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
147 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
Dqe_io.c31 in_be32(&par_io->ioport[port].dir2) : in qe_config_iopin()
32 in_be32(&par_io->ioport[port].dir1); in qe_config_iopin()
46 tmp_val = in_be32(&par_io->ioport[port].podr); in qe_config_iopin()
55 in_be32(&par_io->ioport[port].ppar2): in qe_config_iopin()
56 in_be32(&par_io->ioport[port].ppar1); in qe_config_iopin()
/external/u-boot/drivers/net/fm/
Dtgec_phy.c32 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
43 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
50 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_write()
74 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
85 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
93 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_read()
97 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER) in tgec_mdio_read()
100 return in_be32(&regs->mdio_data) & 0xffff; in tgec_mdio_read()
/external/u-boot/arch/m68k/cpu/mcf5227x/
Dspeed.c63 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
78 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
90 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
93 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
97 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
103 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
112 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
115 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in get_clocks()
/external/u-boot/drivers/serial/
Dserial_xuartlite.c41 if (in_be32(&regs->status) & SR_TX_FIFO_FULL) in uartlite_serial_putc()
54 if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA)) in uartlite_serial_getc()
57 return in_be32(&regs->rx_fifo) & 0xff; in uartlite_serial_getc()
66 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA; in uartlite_serial_pending()
68 return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY); in uartlite_serial_pending()
78 in_be32(&regs->control); in uartlite_serial_probe()
125 in_be32(&regs->control); in _debug_uart_init()
132 while (in_be32(&regs->status) & SR_TX_FIFO_FULL) in _debug_uart_putc()
/external/u-boot/arch/powerpc/cpu/mpc8xxx/
Dlaw.c37 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | in get_law_base_addr()
38 in_be32(LAWBARL_ADDR(idx)); in get_law_base_addr()
40 return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT; in get_law_base_addr()
63 in_be32(LAWAR_ADDR(idx)); in set_law()
74 in_be32(LAWAR_ADDR(idx)); in disable_law()
85 lawar = in_be32(LAWAR_ADDR(i)); in get_law_entry()
164 lawar = in_be32(LAWAR_ADDR(i)); in print_laws()
167 i, in_be32(LAWBARH_ADDR(i)), in print_laws()
168 i, in_be32(LAWBARL_ADDR(i))); in print_laws()
170 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i))); in print_laws()
[all …]
Dsrio.c82 conf_lane = (in_be32((void *)&srds_regs->srdspccr0) in srio_erratum_a004034()
84 init_lane = (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
92 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
103 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
155 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
172 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
192 (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
194 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
213 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) in srio_erratum_a004034()
348 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr); in srio_boot_master_release_slave()
[all …]
/external/u-boot/board/gdsys/common/
Dmiiphybb.c27 in_be32((void *)GPIO0_TCR) | pins->mdio); in io_bb_mdio_active()
37 in_be32((void *)GPIO0_TCR) & ~pins->mdio); in io_bb_mdio_tristate()
48 in_be32((void *)GPIO0_OR) | pins->mdio); in io_bb_set_mdio()
51 in_be32((void *)GPIO0_OR) & ~pins->mdio); in io_bb_set_mdio()
60 *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); in io_bb_get_mdio()
71 in_be32((void *)GPIO0_OR) | pins->mdc); in io_bb_set_mdc()
74 in_be32((void *)GPIO0_OR) & ~pins->mdc); in io_bb_set_mdc()
/external/u-boot/drivers/spi/
Dfsl_espi.c149 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in spi_claim_bus()
155 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
160 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
163 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
167 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
171 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
200 event = in_be32(&espi->event); in fsl_espi_tx()
229 tmpdin = in_be32(&espi->rx); in fsl_espi_rx()
318 event = in_be32(&espi->event); in spi_xfer()
328 event = in_be32(&espi->event); in spi_xfer()
[all …]
/external/u-boot/board/xes/common/
Dfsl_8xxx_pci.c29 u32 devdisr = in_be32(&gur->devdisr); in pci_init_board()
30 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; in pci_init_board()
31 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; in pci_init_board()
32 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; in pci_init_board()
33 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; in pci_init_board()
/external/u-boot/arch/m68k/cpu/mcf532x/
Dspeed.c67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
69 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
153 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
154 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
199 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
232 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
/external/u-boot/board/freescale/t102xrdb/
Dt102xrdb.c49 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in checkboard()
100 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane()
228 u32 val = in_be32(&pgpio->gpdat); in board_mmc_getcd()
239 u32 val = in_be32(&pgpio->gpdat); in board_mmc_getwp()
255 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
261 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
269 val = in_be32(&pgpio->gpdat); in t1023rdb_ctrl()
/external/u-boot/board/keymile/kmp204x/
Dqrio.c22 gprt = in_be32(qrio_base + port_off + GPRT_OFF); in qrio_get_gpio()
35 gprt = in_be32(qrio_base + port_off + GPRT_OFF); in qrio_set_gpio()
52 direct = in_be32(qrio_base + port_off + DIRECT_OFF); in qrio_gpio_direction_output()
67 direct = in_be32(qrio_base + port_off + DIRECT_OFF); in qrio_gpio_direction_input()
80 direct = in_be32(qrio_base + port_off + DIRECT_OFF); in qrio_set_opendrain_gpio()
135 prstcfg = in_be32(qrio_base + PRSTCFG_OFF); in qrio_prstcfg()

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