| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_tcs.cpp | 160 const src_reg &indirect_offset) in emit_input_urb_read() argument
169 indirect_offset); in emit_input_urb_read()
182 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
195 const src_reg &indirect_offset) in emit_output_urb_read() argument
202 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
222 const src_reg &indirect_offset) in emit_urb_write() argument
231 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
260 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
280 first_component, indirect_offset); in nir_emit_intrinsic()
283 imm_offset + 1, 0, indirect_offset); in nir_emit_intrinsic()
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| D | brw_vec4_tcs.h | 62 const src_reg &indirect_offset);
66 const src_reg &indirect_offset);
69 unsigned base_offset, const src_reg &indirect_offset);
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| D | brw_vec4_tes.cpp | 179 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
187 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
190 input_read_header, indirect_offset); in nir_emit_intrinsic()
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| D | brw_reg.h | 235 int indirect_offset:10; /* relative addressing offset */ member
383 reg.indirect_offset = 0; in brw_reg()
1057 reg.indirect_offset = offset; in brw_vec4_indirect()
1067 reg.indirect_offset = offset; in brw_vec1_indirect()
1078 reg.indirect_offset = offset; in brw_VxH_indirect()
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| D | brw_fs_nir.cpp | 2198 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load() local
2235 const fs_reg srcs[] = { icp_handle, indirect_offset }; in emit_gs_input_load()
2273 bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u)); in emit_gs_input_load()
2274 indirect_offset = new_indirect; in emit_gs_input_load()
2506 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2569 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2586 const fs_reg srcs[] = { icp_handle, indirect_offset }; in nir_emit_tcs_intrinsic()
2627 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2647 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2652 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
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| D | brw_shader.h | 82 using brw_reg::indirect_offset;
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_cb_compute.c | 41 GLintptr indirect_offset) in st_dispatch_compute_common() argument
66 info.indirect_offset = indirect_offset; in st_dispatch_compute_common()
79 GLintptr indirect_offset) in st_dispatch_compute_indirect() argument
84 st_dispatch_compute_common(ctx, NULL, NULL, indirect, indirect_offset); in st_dispatch_compute_indirect()
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| D | st_draw.c | 235 GLsizeiptr indirect_offset, in st_indirect_draw_vbo() argument
274 indirect.offset = indirect_offset; in st_indirect_draw_vbo()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_compute.c | 41 GLintptr indirect_offset = brw->compute.num_work_groups_offset; in prepare_indirect_gpgpu_walker() local
44 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0); in prepare_indirect_gpgpu_walker()
45 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4); in prepare_indirect_gpgpu_walker()
46 brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8); in prepare_indirect_gpgpu_walker()
63 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0); in prepare_indirect_gpgpu_walker()
74 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4); in prepare_indirect_gpgpu_walker()
85 brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8); in prepare_indirect_gpgpu_walker()
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| D | brw_draw.c | 227 prim->indirect_offset, 5 * sizeof(GLuint), false); in brw_emit_prim()
232 prim->indirect_offset + 0); in brw_emit_prim()
234 prim->indirect_offset + 4); in brw_emit_prim()
237 prim->indirect_offset + 8); in brw_emit_prim()
240 prim->indirect_offset + 12); in brw_emit_prim()
242 prim->indirect_offset + 16); in brw_emit_prim()
245 prim->indirect_offset + 12); in brw_emit_prim()
849 prim->indirect_offset + (prim->indexed ? 12 : 8); in brw_draw_single_prim()
1016 GLsizeiptr indirect_offset, in brw_draw_indirect_prims() argument
1038 for (i = 0; i < draw_count; ++i, indirect_offset += stride) { in brw_draw_indirect_prims()
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| D | brw_draw.h | 75 GLsizeiptr indirect_offset,
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| /external/mesa3d/src/mesa/vbo/ |
| D | vbo_context.c | 145 GLsizeiptr indirect_offset, in vbo_draw_indirect_prims() argument
167 for (i = 0; i < draw_count; ++i, indirect_offset += stride) { in vbo_draw_indirect_prims()
170 prim[i].indirect_offset = indirect_offset; in vbo_draw_indirect_prims()
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| D | vbo.h | 63 GLsizeiptr indirect_offset; member
116 GLsizeiptr indirect_offset,
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| D | vbo_primitive_restart.c | 201 new_prim.indirect_offset); in vbo_sw_primitive_restart()
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| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_shader.c | 905 unsigned indirect_offset; in ir3_emit_cs_consts() local
915 if (info->indirect_offset & 0xf) { in ir3_emit_cs_consts()
919 indirect_offset = 0; in ir3_emit_cs_consts()
922 info->indirect_offset, 3); in ir3_emit_cs_consts()
925 indirect_offset = info->indirect_offset; in ir3_emit_cs_consts()
929 indirect_offset, 4, NULL, indirect); in ir3_emit_cs_consts()
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| /external/mesa3d/src/amd/common/ |
| D | ac_nir_to_llvm.h | 95 uint32_t indirect_offset; member
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| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_compute.c | 198 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd5_launch_grid()
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| /external/mesa3d/src/gallium/drivers/softpipe/ |
| D | sp_compute.c | 153 info->indirect_offset, in fill_grid_size()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_state.h | 823 unsigned indirect_offset; /**< must be 4 byte aligned */ member
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_program.c | 94 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
119 indirect_offset = qir_ADD(c, indirect_offset, in indirect_uniform_load()
124 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0)); in indirect_uniform_load()
125 indirect_offset = qir_MIN_NOIMM(c, indirect_offset, in indirect_uniform_load()
130 indirect_offset, in indirect_uniform_load()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cmd_buffer.c | 3282 uint64_t indirect_offset; member
3304 va += info->indirect->offset + info->indirect_offset; in radv_emit_draw_packets()
3548 info.indirect_offset = offset; in radv_CmdDrawIndirect()
3568 info.indirect_offset = offset; in radv_CmdDrawIndexedIndirect()
3590 info.indirect_offset = offset; in radv_CmdDrawIndirectCountAMD()
3615 info.indirect_offset = offset; in radv_CmdDrawIndexedIndirectCountAMD()
3638 uint64_t indirect_offset; member
3660 va += info->indirect->offset + info->indirect_offset; in radv_emit_dispatch_packets()
3842 info.indirect_offset = offset; in radv_CmdDispatchIndirect()
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| /external/mesa3d/src/broadcom/compiler/ |
| D | nir_to_vir.c | 86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
111 indirect_offset = vir_ADD(c, indirect_offset, in indirect_uniform_load()
120 indirect_offset); in indirect_uniform_load()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_compute.c | 686 uint64_t va = base_va + info->indirect_offset; in si_setup_tgsi_grid()
772 radeon_emit(cs, info->indirect_offset); in si_emit_dispatch_packets()
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| /external/virglrenderer/src/ |
| D | vrend_renderer.h | 252 uint32_t indirect_offset);
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| D | vrend_decode.c | 1180 uint32_t indirect_handle, indirect_offset; in vrend_decode_launch_grid() local
1191 indirect_offset = get_buf_entry(ctx, VIRGL_LAUNCH_INDIRECT_OFFSET); in vrend_decode_launch_grid()
1192 vrend_launch_grid(ctx->grctx, block, grid, indirect_handle, indirect_offset); in vrend_decode_launch_grid()
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