| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | hazard-inlineasm.mir | 9 # GCN-LABEL: name: hazard-inlineasm
15 name: hazard-inlineasm
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| D | spill-wide-sgpr.ll | 162 ; FIXME: x16 inlineasm seems broken
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| D | inline-asm.ll | 61 ; All inlineasm instructions are assumed to be the maximum size
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| D | fneg-combines.ll | 1839 ; inlineasm tests
1867 ; inlineasm tests
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-stacksave.ll | 10 ; CHECK: inlineasm
14 …call void asm sideeffect "; inlineasm", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x…
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| D | arm64-spill.ll | 6 ; CHECK: inlineasm
12 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
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| D | inlineasm-ldr-pseudo.ll | 3 ; raw text out to the Streamer. We need to actually parse the inlineasm to
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-stacksave.ll | 10 ; CHECK: inlineasm
14 …call void asm sideeffect "; inlineasm", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x…
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| D | arm64-spill.ll | 6 ; CHECK: inlineasm
12 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
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| D | arm64-spill-remarks-treshold-hotness.ll | 21 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
27 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
37 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
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| D | arm64-spill-remarks.ll | 103 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
109 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
119 …call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q…
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| D | inlineasm-ldr-pseudo.ll | 3 ; raw text out to the Streamer. We need to actually parse the inlineasm to
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/ |
| D | upgrade-objcretainrelease-asm.ll | 5 define void @inlineasm() {
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| D | compatibility-3.7.ll | 702 define void @inlineasm(i32 %arg) {
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| D | compatibility-3.6.ll | 658 define void @inlineasm(i32 %arg) {
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| D | compatibility-3.8.ll | 758 define void @inlineasm(i32 %arg) {
|
| /external/llvm/test/Transforms/FunctionImport/ |
| D | inlineasm.ll | 3 ; RUN: opt -module-summary %p/Inputs/inlineasm.ll -o %t2.bc
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/FunctionImport/ |
| D | inlineasm.ll | 3 ; RUN: opt -module-summary %p/Inputs/inlineasm.ll -o %t2.bc
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| /external/llvm/test/CodeGen/ARM/ |
| D | inlineasm-ldr-pseudo.ll | 4 ; raw text out to the Streamer. We need to actually parse the inlineasm to
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | inlineasm-ldr-pseudo.ll | 4 ; raw text out to the Streamer. We need to actually parse the inlineasm to
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | inline-asm.ll | 61 ; All inlineasm instructions are assumed to be the maximum size
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| /external/mesa3d/src/amd/common/ |
| D | ac_llvm_build.c | 342 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false); in ac_build_optimization_barrier() local
343 LLVMBuildCall(builder, inlineasm, NULL, 0, ""); in ac_build_optimization_barrier()
346 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false); in ac_build_optimization_barrier() local
356 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, ""); in ac_build_optimization_barrier()
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| /external/llvm/test/Bitcode/ |
| D | compatibility-3.7.ll | 702 define void @inlineasm(i32 %arg) {
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| D | compatibility-3.6.ll | 658 define void @inlineasm(i32 %arg) {
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| D | compatibility-3.8.ll | 758 define void @inlineasm(i32 %arg) {
|