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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td18 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
22 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
26 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
32 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
36 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
40 defm I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
44 defm I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
48 defm I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
65 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
70 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
43 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
47 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
[all …]
DX86InstrFPStack.td76 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
78 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
80 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
82 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
84 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
86 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
88 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
90 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
92 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
116 def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>;
[all …]
DX86InstrFormats.td119 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
130 dag InOperandList = ins;
183 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
185 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
189 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
191 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
195 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
197 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
201 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
203 : X86Inst<o, f, Imm16, outs, ins, asm> {
[all …]
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
46 (ins GR64:$src1, i8imm:$src2),
52 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
54 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreInstrFormats.td13 class InstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag InOperandList = ins;
25 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
26 : InstXCore<outs, ins, asmstr, pattern>;
32 class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern>
33 : InstXCore<outs, ins, asmstr, pattern> {
37 class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
38 : InstXCore<outs, ins, asmstr, pattern> {
42 class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
43 : InstXCore<outs, ins, asmstr, pattern> {
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td73 def EVLDD : EVXForm_D<769, (outs gprc:$RT), (ins spe8dis:$dst),
75 def EVLDW : EVXForm_D<771, (outs gprc:$RT), (ins spe8dis:$dst),
77 def EVLDH : EVXForm_D<773, (outs gprc:$RT), (ins spe8dis:$dst),
79 def EVLHHESPLAT : EVXForm_D<777, (outs gprc:$RT), (ins spe2dis:$dst),
81 def EVLHHOUSPLAT : EVXForm_D<781, (outs gprc:$RT), (ins spe2dis:$dst),
83 def EVLHHOSSPLAT : EVXForm_D<783, (outs gprc:$RT), (ins spe2dis:$dst),
85 def EVLWHE : EVXForm_D<785, (outs gprc:$RT), (ins spe4dis:$dst),
87 def EVLWHOU : EVXForm_D<789, (outs gprc:$RT), (ins spe4dis:$dst),
89 def EVLWHOS : EVXForm_D<791, (outs gprc:$RT), (ins spe4dis:$dst),
91 def EVLWWSPLAT : EVXForm_D<793, (outs gprc:$RT), (ins spe4dis:$dst),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td141 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
145 def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
149 def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
153 def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
157 def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
160 def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
164 def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
168 def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
171 def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
175 def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSystem.td18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
47 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
[all …]
DX86InstrFPStack.td78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
121 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
[all …]
DX86InstrControl.td24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV60.td42 class CVI_VA_Resource<dag outs, dag ins, string asmstr,
45 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
48 class CVI_VA_DV_Resource<dag outs, dag ins, string asmstr,
51 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA_DV>,
54 class CVI_VX_Resource_long<dag outs, dag ins, string asmstr,
57 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
60 class CVI_VX_Resource_late<dag outs, dag ins, string asmstr,
63 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
66 class CVI_VX_Resource<dag outs, dag ins, string asmstr,
69 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrFormats.td13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag InOperandList = ins;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreInstrFormats.td13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag InOperandList = ins;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrSystem.td18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
31 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
35 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
46 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
50 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
[all …]
DX86InstrFPStack.td78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
121 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
[all …]
DX86InstrControl.td24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
26 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
28 def RETW : I <0xC3, RawFrm, (outs), (ins),
30 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
32 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
34 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
36 def LRETL : I <0xCB, RawFrm, (outs), (ins),
38 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
40 def LRETW : I <0xCB, RawFrm, (outs), (ins),
42 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
61 dag InOperandList = ins;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
61 dag InOperandList = ins;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430InstrFormats.td54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
61 dag InOperandList = ins;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
[all …]
/external/python/cpython2/Modules/
Dfcntlmodule.c426 ins(PyObject* d, char* symbol, long value) in ins() function
436 #define INS(x) if (ins(d, #x, (long)x)) return -1
441 if (ins(d, "LOCK_SH", (long)LOCK_SH)) return -1; in all_ins()
442 if (ins(d, "LOCK_EX", (long)LOCK_EX)) return -1; in all_ins()
443 if (ins(d, "LOCK_NB", (long)LOCK_NB)) return -1; in all_ins()
444 if (ins(d, "LOCK_UN", (long)LOCK_UN)) return -1; in all_ins()
447 if (ins(d, "LOCK_MAND", (long)LOCK_MAND)) return -1; in all_ins()
450 if (ins(d, "LOCK_READ", (long)LOCK_READ)) return -1; in all_ins()
453 if (ins(d, "LOCK_WRITE", (long)LOCK_WRITE)) return -1; in all_ins()
456 if (ins(d, "LOCK_RW", (long)LOCK_RW)) return -1; in all_ins()
[all …]
/external/python/cpython2/RISCOS/Modules/
Driscosmodule.c407 ins(PyObject *module, char *symbol, long value) in ins() function
417 if (ins(d, "F_OK", (long)F_OK)) return -1; in all_ins()
420 if (ins(d, "R_OK", (long)R_OK)) return -1; in all_ins()
423 if (ins(d, "W_OK", (long)W_OK)) return -1; in all_ins()
426 if (ins(d, "X_OK", (long)X_OK)) return -1; in all_ins()
429 if (ins(d, "NGROUPS_MAX", (long)NGROUPS_MAX)) return -1; in all_ins()
432 if (ins(d, "TMP_MAX", (long)TMP_MAX)) return -1; in all_ins()
435 if (ins(d, "WCONTINUED", (long)WCONTINUED)) return -1; in all_ins()
438 if (ins(d, "WNOHANG", (long)WNOHANG)) return -1; in all_ins()
441 if (ins(d, "WUNTRACED", (long)WUNTRACED)) return -1; in all_ins()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrFormats.td45 class InstSystemZ<bits<16> op, Format f, dag outs, dag ins> : Instruction {
54 dag InOperandList = ins;
57 class I8<bits<8> op, Format f, dag outs, dag ins, string asmstr,
59 : InstSystemZ<0, f, outs, ins> {
67 class I12<bits<12> op, Format f, dag outs, dag ins, string asmstr,
69 : InstSystemZ<0, f, outs, ins> {
77 class I16<bits<16> op, Format f, dag outs, dag ins, string asmstr,
79 : InstSystemZ<op, f, outs, ins> {
84 class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
85 : I8<op, RRForm, outs, ins, asmstr, pattern>;
[all …]
DSystemZInstrInfo.td71 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
74 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
96 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DGenericOpcodes.td25 let InOperandList = (ins type1:$src);
33 let InOperandList = (ins type1:$src);
41 let InOperandList = (ins type1:$src);
50 let InOperandList = (ins type1:$src);
56 let InOperandList = (ins);
62 let InOperandList = (ins variable_ops);
68 let InOperandList = (ins unknown:$src2);
74 let InOperandList = (ins unknown:$src);
80 let InOperandList = (ins type1:$src);
86 let InOperandList = (ins type1:$src);
[all …]

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