| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| D | intel_batchbuffer.c | 36 intel_batchbuffer_reset(struct intel_context *intel);
39 intel_batchbuffer_init(struct intel_context *intel) in intel_batchbuffer_init() argument
41 intel_batchbuffer_reset(intel); in intel_batchbuffer_init()
43 intel->batch.cpu_map = malloc(intel->maxBatchSize); in intel_batchbuffer_init()
44 intel->batch.map = intel->batch.cpu_map; in intel_batchbuffer_init()
48 intel_batchbuffer_reset(struct intel_context *intel) in intel_batchbuffer_reset() argument
50 if (intel->batch.last_bo != NULL) { in intel_batchbuffer_reset()
51 drm_intel_bo_unreference(intel->batch.last_bo); in intel_batchbuffer_reset()
52 intel->batch.last_bo = NULL; in intel_batchbuffer_reset()
54 intel->batch.last_bo = intel->batch.bo; in intel_batchbuffer_reset()
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| D | intel_tris.c | 65 intel_flush_inline_primitive(struct intel_context *intel) in intel_flush_inline_primitive() argument
67 GLuint used = intel->batch.used - intel->prim.start_ptr; in intel_flush_inline_primitive()
69 assert(intel->prim.primitive != ~0); in intel_flush_inline_primitive()
76 intel->batch.map[intel->prim.start_ptr] = in intel_flush_inline_primitive()
77 _3DPRIMITIVE | intel->prim.primitive | (used - 2); in intel_flush_inline_primitive()
82 intel->batch.used = intel->prim.start_ptr; in intel_flush_inline_primitive()
85 intel->prim.primitive = ~0; in intel_flush_inline_primitive()
86 intel->prim.start_ptr = 0; in intel_flush_inline_primitive()
87 intel->prim.flush = 0; in intel_flush_inline_primitive()
90 static void intel_start_inline(struct intel_context *intel, uint32_t prim) in intel_start_inline() argument
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| D | intel_context.c | 88 const struct intel_context *const intel = intel_context(ctx); in intelGetString() local
96 (GLubyte *) i915_get_renderer_string(intel->intelScreen->deviceID); in intelGetString()
108 struct intel_context *intel = intel_context(ctx); in intel_flush_front() local
109 __DRIcontext *driContext = intel->driContext; in intel_flush_front()
111 __DRIscreen *const screen = intel->intelScreen->driScrnPriv; in intel_flush_front()
113 if (intel->front_buffer_dirty && _mesa_is_winsys_fbo(ctx->DrawBuffer)) { in intel_flush_front()
122 intel->front_buffer_dirty = false; in intel_flush_front()
128 intel_update_image_buffers(struct intel_context *intel, __DRIdrawable *drawable);
137 intel_query_dri2_buffers(struct intel_context *intel,
143 intel_process_dri2_buffer(struct intel_context *intel,
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| D | intel_batchbuffer.h | 23 void intel_batchbuffer_init(struct intel_context *intel);
24 void intel_batchbuffer_free(struct intel_context *intel);
26 int _intel_batchbuffer_flush(struct intel_context *intel,
29 #define intel_batchbuffer_flush(intel) \ argument
30 _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
38 void intel_batchbuffer_data(struct intel_context *intel,
41 bool intel_batchbuffer_emit_reloc(struct intel_context *intel,
46 bool intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
51 void intel_batchbuffer_emit_mi_flush(struct intel_context *intel);
70 intel_batchbuffer_space(struct intel_context *intel) in intel_batchbuffer_space() argument
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| D | intel_buffer_objects.c | 48 intel_bufferobj_alloc_buffer(struct intel_context *intel, in intel_bufferobj_alloc_buffer() argument
51 intel_obj->buffer = drm_intel_bo_alloc(intel->bufmgr, "bufferobj", in intel_bufferobj_alloc_buffer()
123 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_data() local
153 intel_bufferobj_alloc_buffer(intel, intel_obj); in intel_bufferobj_data()
177 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_subdata() local
203 drm_intel_bo_references(intel->batch.bo, intel_obj->buffer); in intel_bufferobj_subdata()
209 intel_bufferobj_alloc_buffer(intel, intel_obj); in intel_bufferobj_subdata()
216 drm_intel_bo_alloc(intel->bufmgr, "subdata temp", size, 64); in intel_bufferobj_subdata()
220 intel_emit_linear_blit(intel, in intel_bufferobj_subdata()
243 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_get_subdata() local
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| D | i830_vtbl.c | 46 static bool i830_check_vertex_size(struct intel_context *intel,
53 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
54 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
55 intel->vertex_attr_count++; \
61 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
62 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
63 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
64 intel->vertex_attr_count++; \
72 i830_render_prevalidate(struct intel_context *intel) in i830_render_prevalidate() argument
77 i830_render_start(struct intel_context *intel) in i830_render_start() argument
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| D | i915_vtbl.c | 53 i915_render_prevalidate(struct intel_context *intel) in i915_render_prevalidate() argument
55 struct i915_context *i915 = i915_context(&intel->ctx); in i915_render_prevalidate()
61 i915_render_start(struct intel_context *intel) in i915_render_start() argument
63 intel_prepare_render(intel); in i915_render_start()
68 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim) in i915_reduced_primitive_state() argument
70 struct i915_context *i915 = i915_context(&intel->ctx); in i915_reduced_primitive_state()
78 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple) in i915_reduced_primitive_state()
87 i915->intel.reduced_primitive = rprim; in i915_reduced_primitive_state()
90 INTEL_FIREVERTICES(intel); in i915_reduced_primitive_state()
102 i915_check_vertex_size(struct intel_context *intel, GLuint expected) in i915_check_vertex_size() argument
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| D | intel_render.c | 110 intelDmaPrimitive(struct intel_context *intel, GLenum prim) in intelDmaPrimitive() argument
114 INTEL_FIREVERTICES(intel); in intelDmaPrimitive()
115 intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]); in intelDmaPrimitive()
116 intel_set_prim(intel, hw_prim[prim]); in intelDmaPrimitive()
121 static inline GLuint intel_get_vb_max(struct intel_context *intel) in intel_get_vb_max() argument
125 if (intel->intelScreen->no_vbo) { in intel_get_vb_max()
126 ret = intel->batch.bo->size - INTEL_NO_VBO_STATE_RESERVED; in intel_get_vb_max()
129 ret /= (intel->vertex_size * 4); in intel_get_vb_max()
133 static inline GLuint intel_get_current_max(struct intel_context *intel) in intel_get_current_max() argument
137 if (intel->intelScreen->no_vbo) { in intel_get_current_max()
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| D | intel_context.h | 45 #define TAG(x) intel##x
78 extern void intelFallback(struct intel_context *intel, GLbitfield bit,
80 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode ) argument
119 void (*destroy) (struct intel_context * intel);
120 void (*emit_state) (struct intel_context * intel);
121 void (*finish_batch) (struct intel_context * intel);
122 void (*new_batch) (struct intel_context * intel);
123 void (*emit_invarient_state) (struct intel_context * intel);
124 void (*update_texture_state) (struct intel_context * intel);
126 void (*render_start) (struct intel_context * intel);
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| D | intel_syncobj.c | 48 struct intel_context *intel; member
69 intel_fence_insert(struct intel_context *intel, struct intel_fence *fence) in intel_fence_insert() argument
74 intel_batchbuffer_emit_mi_flush(intel); in intel_fence_insert()
75 fence->batch_bo = intel->batch.bo; in intel_fence_insert()
77 intel_batchbuffer_flush(intel); in intel_fence_insert()
109 intel_fence_client_wait_locked(struct intel_context *intel, struct intel_fence *fence, in intel_fence_client_wait_locked() argument
140 intel_fence_client_wait(struct intel_context *intel, struct intel_fence *fence, in intel_fence_client_wait() argument
146 ret = intel_fence_client_wait_locked(intel, fence, timeout); in intel_fence_client_wait()
153 intel_fence_server_wait(struct intel_context *intel, struct intel_fence *fence) in intel_fence_server_wait() argument
187 struct intel_context *intel = intel_context(ctx); in intel_gl_fence_sync() local
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| D | i915_context.h | 247 struct intel_context intel; member
265 INTEL_FIREVERTICES( &(i915)->intel ); \
271 INTEL_FIREVERTICES( &(i915)->intel ); \
285 i915_state_draw_region(struct intel_context *intel,
296 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
297 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
299 intel->vertex_attr_count++; \
305 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
306 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
307 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
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| D | intel_mipmap_tree.c | 64 intel_miptree_create_layout(struct intel_context *intel, in intel_miptree_create_layout() argument
107 intel_get_texture_alignment_unit(intel, mt->format, in intel_miptree_create_layout()
110 if (intel->is_945) in intel_miptree_create_layout()
122 intel_miptree_choose_tiling(struct intel_context *intel, in intel_miptree_choose_tiling() argument
157 intel_miptree_create(struct intel_context *intel, in intel_miptree_create() argument
172 mt = intel_miptree_create_layout(intel, target, format, in intel_miptree_create()
185 uint32_t tiling = intel_miptree_choose_tiling(intel, format, width0, in intel_miptree_create()
190 mt->region = intel_region_alloc(intel->intelScreen, in intel_miptree_create()
201 if (y_or_x && mt->region->bo->size >= intel->max_gtt_map_object_size) { in intel_miptree_create()
206 mt->region = intel_region_alloc(intel->intelScreen, in intel_miptree_create()
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| D | intel_fbo.c | 91 struct intel_context *intel = intel_context(ctx); in intel_map_renderbuffer() local
106 intel_prepare_render(intel); in intel_map_renderbuffer()
116 intel_miptree_map(intel, irb->mt, irb->mt_level, irb->mt_layer, in intel_map_renderbuffer()
139 struct intel_context *intel = intel_context(ctx); in intel_unmap_renderbuffer() local
152 intel_miptree_unmap(intel, irb->mt, irb->mt_level, irb->mt_layer); in intel_unmap_renderbuffer()
158 struct intel_context *intel = intel_context(ctx); in intel_renderbuffer_format() local
167 return intel->ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D, in intel_renderbuffer_format()
194 struct intel_context *intel = intel_context(ctx); in intel_alloc_private_renderbuffer_storage() local
212 irb->mt = intel_miptree_create_for_renderbuffer(intel, rb->Format, in intel_alloc_private_renderbuffer_storage()
238 struct intel_context *intel = intel_context(ctx); in intel_image_target_renderbuffer_storage() local
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| D | i830_context.c | 66 struct intel_context *intel = &i830->intel; in i830CreateContext() local
67 struct gl_context *ctx = &intel->ctx; in i830CreateContext()
77 if (!intelInitContext(intel, __DRI_API_OPENGL, in i830CreateContext()
88 _math_matrix_ctr(&intel->ViewportMatrix); in i830CreateContext()
97 if (intel->no_rast) in i830CreateContext()
98 FALLBACK(intel, INTEL_FALLBACK_USER, 1); in i830CreateContext()
100 intel->ctx.Const.MaxTextureUnits = I830_TEX_UNITS; in i830CreateContext()
101 intel->ctx.Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = I830_TEX_UNITS; in i830CreateContext()
102 intel->ctx.Const.MaxTextureCoordUnits = I830_TEX_UNITS; in i830CreateContext()
121 intel->verts = TNL_CONTEXT(ctx)->clipspace.vertex_buf; in i830CreateContext()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_object_purgeable.c | 74 struct intel_texture_object *intel; in intel_texture_object_purgeable() local
79 intel = intel_texture_object(obj); in intel_texture_object_purgeable()
80 if (intel->mt == NULL || intel->mt->bo == NULL) in intel_texture_object_purgeable()
83 return intel_buffer_purgeable(intel->mt->bo); in intel_texture_object_purgeable()
91 struct intel_renderbuffer *intel; in intel_render_object_purgeable() local
96 intel = intel_renderbuffer(obj); in intel_render_object_purgeable()
97 if (intel->mt == NULL) in intel_render_object_purgeable()
100 return intel_buffer_purgeable(intel->mt->bo); in intel_render_object_purgeable()
120 struct intel_buffer_object *intel = intel_buffer_object(obj); in intel_buffer_object_unpurgeable() local
124 if (!intel->buffer) in intel_buffer_object_unpurgeable()
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| /external/u-boot/doc/device-tree-bindings/video/ |
| D | intel-gma.txt | 9 - compatible : "intel,gma";
12 - intel,dp-hotplug : values for digital port hotplug, one cell per value for
14 - intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D
15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
18 - intel,panel-power-up-delay : T1+T2 time sequence
19 - intel,panel-power-down-delay : T3 time sequence
20 - intel,panel-power-backlight-on-delay : T5 time sequence
21 - intel,panel-power-backlight-off-delay : Tx time sequence
23 - intel,cpu-backlight : Value for CPU Backlight PWM
24 - intel,pch-backlight : Value for PCH Backlight PWM
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| /external/u-boot/arch/x86/dts/ |
| D | cougarcanyon2.dts | 8 #include <dt-bindings/interrupt-router/intel-irq.h>
18 compatible = "intel,cougarcanyon2", "intel,chiefriver";
38 compatible = "intel,core-gen3";
40 intel,apic-id = <0>;
45 compatible = "intel,core-gen3";
47 intel,apic-id = <1>;
52 compatible = "intel,core-gen3";
54 intel,apic-id = <2>;
59 compatible = "intel,core-gen3";
61 intel,apic-id = <3>;
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| D | chromebook_link.dts | 14 compatible = "google,link", "intel,celeron-ivybridge";
32 compatible = "intel,core-gen3";
34 intel,apic-id = <0>;
39 compatible = "intel,core-gen3";
41 intel,apic-id = <1>;
46 compatible = "intel,core-gen3";
48 intel,apic-id = <2>;
53 compatible = "intel,core-gen3";
55 intel,apic-id = <3>;
65 intel,duplicate-por;
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| D | chromebook_samus.dts | 14 compatible = "google,samus", "intel,broadwell";
32 compatible = "intel,core-i3-gen5";
34 intel,apic-id = <0>;
35 intel,slow-ramp = <3>;
40 compatible = "intel,core-i3-gen5";
42 intel,apic-id = <1>;
47 compatible = "intel,core-i3-gen5";
49 intel,apic-id = <2>;
54 compatible = "intel,core-i3-gen5";
56 intel,apic-id = <3>;
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| D | bayleybay.dts | 10 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "intel,bayleybay", "intel,baytrail";
42 compatible = "intel,baytrail-cpu";
44 intel,apic-id = <0>;
49 compatible = "intel,baytrail-cpu";
51 intel,apic-id = <2>;
56 compatible = "intel,baytrail-cpu";
58 intel,apic-id = <4>;
63 compatible = "intel,baytrail-cpu";
65 intel,apic-id = <6>;
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| D | baytrail_som-db5800-som-6867.dts | 11 #include <dt-bindings/interrupt-router/intel-irq.h>
20 compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
84 compatible = "intel,baytrail-cpu";
86 intel,apic-id = <0>;
91 compatible = "intel,baytrail-cpu";
93 intel,apic-id = <2>;
98 compatible = "intel,baytrail-cpu";
100 intel,apic-id = <4>;
105 compatible = "intel,baytrail-cpu";
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| D | conga-qeval20-qa3-e3845.dts | 11 #include <dt-bindings/interrupt-router/intel-irq.h>
20 compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
32 compatible = "intel,x86-pinctrl";
72 compatible = "intel,baytrail-cpu";
74 intel,apic-id = <0>;
79 compatible = "intel,baytrail-cpu";
81 intel,apic-id = <2>;
86 compatible = "intel,baytrail-cpu";
88 intel,apic-id = <4>;
93 compatible = "intel,baytrail-cpu";
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| D | dfi-bt700.dtsi | 9 #include <dt-bindings/interrupt-router/intel-irq.h>
21 compatible = "intel,x86-pinctrl";
70 compatible = "intel,baytrail-cpu";
72 intel,apic-id = <0>;
77 compatible = "intel,baytrail-cpu";
79 intel,apic-id = <2>;
84 compatible = "intel,baytrail-cpu";
86 intel,apic-id = <4>;
91 compatible = "intel,baytrail-cpu";
93 intel,apic-id = <6>;
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| D | cherryhill.dts | 9 #include <dt-bindings/interrupt-router/intel-irq.h>
18 compatible = "intel,cherryhill", "intel,braswell";
41 intel,apic-id = <0>;
48 intel,apic-id = <2>;
55 intel,apic-id = <4>;
62 intel,apic-id = <6>;
77 compatible = "intel,pch9";
80 compatible = "intel,irq-router";
81 intel,pirq-config = "ibase";
82 intel,ibase-offset = <0x50>;
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| /external/libxcam/ |
| D | AUTHORS | 4 Wind Yuan <feng.yuan@intel.com>
7 Fei Wang <feix.w.wang@intel.com>
8 Jia Meng <jia.meng@intel.com>
9 John Ye <john.ye@intel.com>
10 Juan Zhao <juan.j.zhao@intel.com>
12 Sameer Kibey <sameer.kibey@intel.com>
13 Shincy Tu <shincy.tu@intel.com>
14 Wei Zong <wei.zong@intel.com>
15 Yan Zhang <yan.y.zhang@intel.com>
16 Yao Wang <yao.y.wang@intel.com>
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